ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 450
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ATUC128L4U
Manufacturer Part Number
ATUC128L4U
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.ATUC128L4U.pdf
(960 pages)
4.ATUC128L4U.pdf
(92 pages)
Specifications of ATUC128L4U
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATUC128L4U-U
Manufacturer:
ATMEL
Quantity:
3 006
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- ATUC128L4U PDF datasheet #3
- ATUC128L4U PDF datasheet #4
- Current page: 450 of 960
- Download datasheet (15Mb)
20.6.5.1
20.6.5.2
20.6.5.3
20.6.5.4
20.6.5.5
Figure 20-21. Header Transmission
20.6.5.6
32142A–12/2011
Baud Rate
TXRDY
LINIR
LINIR
Clock
Write
TXD
Modes of operation
Receiver and Transmitter Control
Baud Rate Configuration
Character Transmission and Reception
Header Transmission (Master Node Configuration)
Header Reception (Slave Node Configuration)
ID
13 dominant bits (at 0)
customizable response data lengths, and requires minimal CPU resources. Writing 0xA (master)
or 0xB (slave) to MR.MODE enables this mode.
Changing LIN mode after initial configuration has to be followed by a transceiver software reset
in order to avoid unpredictable behavior.
See Section “20.6.2” on page 439.
The LIN nodes baud rate is configured in the Baud Rate Generator Register (BRGR),
tion “20.6.1.1” on page 437.
See
All LIN frames start with a header sent by the master. As soon as the identifier has been written
to the Identifier Character field in the LIN Identifier Register (LINIR.IDCHR), TXRDY is cleared
and the header is sent. The header consists of a Break, Sync, and Identifier field. TXRDY is set
when the identifier has been transferred into the transmitters shift register.
The Break field consists of 13 dominant bits, the break, and one recessive bit, the break delim-
iter. The Sync field is the character 0x55. The Identifier field contains the Identifier as written to
IDCHR. The identifier parity bits can be generated automatically (see
The USART stays idle until it detects a break field, consisting of at least 11 consecutive domi-
nant bits (zeroes) on the bus. A received break will set the Lin Break bit (CSR.LINBK). The Sync
field is used to synchronize the baud rate (see
Identifier bit (CSR.LINID) is set when the Identifier has been received. The Identifier parity bits
can be automatically checked (see
and LINID.
Break Field
”Transmitter Operations” on page
1 recessive bit
Delimiter
Break
(at 1)
Start
Bit
1
Section
0
Synch Byte = 0x55
440, and
1
0
20.6.5.8). Writing a one to RSTSTA will clear LINBK
1
Section
0
”Receiver Operations” on page
1
ATUC64/128/256L3/4U
0
20.6.5.7). IDCHR is updated and the LIN
Stop
Bit
Start
Bit
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7
Section
20.6.5.8).
442.
Stop
See Sec-
Bit
450
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