ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 125

• Manufacturer Part Number: ATxmega128A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.5
12.6
12.6.1
8077H–AVR–12/09
Interrupt level
Interrupt priority
Static priority
rupt execution response time is increased by five clock cycles. In addition the response time is
increased by the start-up time from the selected sleep mode.
A return from an interrupt handling routine takes five clock cycles. During these five clock cycles,
the program counter is popped from the stack and the stack pointer is incremented.
The interrupt level is independently selected for each interrupt source. For any interrupt request,
the PMIC also receives the interrupt level for the interrupt. The interrupt levels and their corre-
sponding bit values for the interrupt level configuration of all interrupts is shown in
Table 12-1.
The interrupt level of an interrupt request is compared against the current level and status of the
interrupt controller. An interrupt request on higher level will interrupt any ongoing interrupt han-
dler from a lower level interrupt. When returning from the higher level interrupt handler, the
execution of the lower level interrupt handler will continue.
Within each interrupt level, all interrupts have a priority. When several interrupt requests are
pending, the order of which interrupts are acknowledged is decided both by the level and the pri-
ority of the interrupt request. Interrupts can be organized in a static or dynamic (round-robin)
priority scheme. High and Medium level interrupts and the NMI will always have static priority.
For Low level interrupts, static or dynamic priority scheduling can be selected.
Interrupt vectors (IVEC) are located at fixed addresses. For static priority, the interrupt vector
address decides the priority within one interrupt level where the lowest interrupt vector address
has the highest priority. Refer to the device data sheet for interrupt vector table with the base
address for all modules and peripherals with interrupt. Refer to the interrupt vector summary of
each module and peripheral in this manual for a list of interrupts and their corresponding offset
address within the different modules and peripherals.
Interrupt level
configuration
00
01
10
11
Interrupt level
Group Configuration
MED
OFF
LO
HI
Description
Interrupt disabled.
Low level interrupt
Medium level interrupt
High level interrupt
XMEGA A
Table
12-1.
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