ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 375
ATxmega128A1
Manufacturer Part Number
ATxmega128A1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A1
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
78
Ext Interrupts
78
Usb Speed
No
Usb Interface
No
Spi
12
Twi (i2c)
4
Uart
8
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
8
Output Compare Channels
24
Input Capture Channels
24
Pwm Channels
24
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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30.11.4
30.11.4.1
8077H–AVR–12/09
EEPROM Programming
Addressing the EEPROM
1.
2.
3.
during self-programming.
The result will be available in the NVM DATA0 register. The CPU is halted during the complete
execution of the command.
The EEPROM can be read and written from application code in any part of the Flash. Its is both
byte and page accessible. This means that either one byte or one page can be written to the
EEPROM at once. One byte is read from the EEPROM during read.
The EEPROM can be accessed through the NVM controller (I/O mapped), similar to the Flash
Program memory, or it can be memory mapped into the Data Memory space to be accessed
similar to SRAM.
When accessing the EEPROM through the NVM Controller, the NVM Address (ADDR) register
is used to address the EEPROM, while the NVM Data (DATA) register is used to store or load
EEPROM data.
For EEPROM page programming the ADDR register can be treated as having two section. The
least significant bits address the bytes within a page, while the most significant bits address the
page within the EEPROM. This is shown in
page (E2BYTE) is held by the bits [1:BYTEMSB] in the ADDR register. The remaining bits
[PAGEMSB:BYTEMSB+1] in the ADDR register holds the EEPROM page address (E2PAGE).
Together E2BYTE and E2PAGE holds an absolute address to a byte in the EEPROM. The size
of E2WORD and E2PAGE will depend on the page and flash size in the device, refer to the
device data sheet for details on this.
Load the NVM ADDR registers with the address to the fuse byte to read.
Load the NVM CMD register with the Read Fuses command.
Set the CMDEX bit in the NVM CTRLA register. This requires the timed CCP sequence
Figure 30-3 on page
376. The byte address in the
XMEGA A
375
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