ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 344

• Manufacturer Part Number: ATxmega128A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

29. Program and Debug Interface
29.1
29.2
8077H–AVR–12/09
Features
Overview
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The Program and Debug Interface (PDI) is an Atmel proprietary interface for external program-
ming and on-chip debugging of the device.
The PDI supports high-speed programming of all Non-Volatile Memory (NVM) spaces; Flash,
EEPOM, Fuses, Lockbits and the User Signature Row. This is done by accessing the NVM Con-
troller, and executing NVM Controller commands as described in Memory Programming.
The On-Chip Debug (OCD) system supports fully intrusive operation. During debugging no soft-
ware or hardware resources in the device is used (except for four I/O pins required if JTAG
connection is used). The OCD system has full program flow control, supports unlimited number
of program and data breakpoints and has full access (read/write) to all memories.
Both programming and debugging can be done through two physical interfaces. The primary
interface is the PDI Physical. This is a 2-pin interface using the Reset pin for the clock input
Program and Debug Interface (PDI)
Programming Features
Debugging Features
JTAG Interface
– 2-pin interface for external programming and on-chip debugging
– Uses Reset pin and dedicated Test pin
– Flexible communication protocol
– 8 Flexible instructions.
– Minimal protocol overhead.
– Fast
– Reliable
– Non-Intrusive Operation
– Complete Program Flow Control
– 1 dedicated program address breakpoint or symbolic breakpoint for AVR studio/emulator
– 4 Hardware Breakpoints
– Unlimited Number of User Program Breakpoints
– Uses CPU for Accessing I/O, Data, and Program
– High Speed Operation
– JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard
– Programming features as for PDI
– On-chip debug features as for PDI
• No I/O pins required during programming or debugging
• 10 MHz programming clock at 1.8V V
• Built in error detection and handling
• Uses no hardware or software resource
• Symbolic Debugging Support in Hardware
• Go, Stop, Reset, Step into, Step over, Step out, Run-to-Cursor
• No limitation on system clock frequency
CC
XMEGA A
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