ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 342

• Manufacturer Part Number: ATxmega128A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.5.2
28.5.2.1
28.5.2.2
28.5.2.3
28.5.3
28.5.4
28.6
28.6.1
8077H–AVR–12/09
Boundary-scan chain
Device Identification register
Boundary-scan Chain
PDICOM data register
Scanning the Port Pins
Version
Part Number
Manufacturer ID
Figure 28-3. Device Identification register
Version is a 4-bit number identifying the revision of the component. The JTAG version number
follows the revision of the device. Revision A is 0x0, revision B is 0x1 and so on.
The part number is a 16-bit code identifying the component. Refer to the device data sheets to
find the correct number.
The Manufacturer ID is an 11-bit code identifying the manufacturer. For Atmel this code is
11x01F.
The Boundary-scan Chain has the capability of driving and observing the logic levels on all I/O
pins. Refer to
The PDICOM data register is a 9-bit wide register used for serial-to-parallel - and parallel-to-
serial conversion of data between the JTAG TAP and the PDI. For details refer to
”Program and Debug Interface” on page
The Boundary-scan chain has the capability of driving and observing the logic levels on the I/O
pins. To ensure a predictable chip behavior during and after the instructions EXTEST, CLAMP
and HIGHZ, the chip is automatically put in reset. During active reset, the external oscillators,
analog modules, and non-default port settings (like pull-up/down, bus-keeper, wired-AND/-OR)
are disabled. It should be noted that the current chip - and port state is unaffected by the SAM-
PLE and PRELOAD instructions.
Figure 28-4 on page 343
This cell is able to control and observe both pin direction and pin value via a two-stage Shift
Register. When no alternate port function is present, Output control corresponds to the DIR reg-
ister value, Output data corresponds to the OUT register value, and Input data corresponds to
the IN register value (tapped before the input inverter and - synchronizer). Mode represents
either an active CLAMP or EXTEST instruction, while ShiftDR is set when the TAP controller is
in its Shift-DR state.
Bit
Device ID
Section 28.6 ”Boundary-scan chain” on page 342
MSB
31
Version
4 bits
28
shows the Boundary-scan Cell used for all the bi-directional port pins.
27
344.
Part Number
16 bits
12
for a complete description.
11
Manufacturer ID
11 bits
XMEGA A
1
Section 29.
LSB
1 bit
0
1
342