ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 347

• Manufacturer Part Number: ATxmega128A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

29.3.3.1
29.3.4
8077H–AVR–12/09
Serial transmission and reception
Characters
Table 29-1.
Three different characters, DATA, BREAK and IDLE, are used. The BREAK character is equal
to 12 bit-length of low level. The IDLE character is equal to 12 bit-length of high level. Both the
BREAK and the IDLE character can be extended beyond the bit-length of 12.
Figure 29-5. Characters and timing for the PDI Physical.
The PDI physical layer is either in Transmit (TX) or Receive (RX) mode of operation. By default
it is in RX mode, waiting for a start bit.
The programmer and the PDI operate synchronously on the PDI_CLK provided by the program-
mer. The dependency between the clock edges and data sampling or data change is fixed. As
illustrated in
is always set up (changed) on the falling edge of PDI_CLK, while data is always sampled on the
rising edge of PDI_CLK.
Figure 29-6. Changing and sampling of data.
St
(0-7)
P
Sp1
Sp2
Start bit, always low.
Data bits (0 to 7)
Parity bit, even parity is used
Stop bit 1, always high.
Stop bit 2, always high.
Figure 29-6 on page
PD I_DATA
PDI_CLK
START
0
1
347, output data (either from the programmer or from the PDI)
2
Sam ple
3
1 BREAK character
1 DATA character
1 IDLE character
BREAK
4
IDLE
5
6
Sam ple
7
P
STOP
Sam ple
XMEGA A
347