ATxmega128D3 Atmel Corporation, ATxmega128D3 Datasheet - Page 192

• Manufacturer Part Number: ATxmega128D3
• Manufacturer: Atmel Corporation

Specifications of ATxmega128D3

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 200
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 18
• Input Capture Channels: 18
• Pwm Channels: 18
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

16.11 Register Summary - TWI
16.12 Register Summary - TWI Master
16.13 Register Summary - TWI Slave
16.14 Interrupt Vector Summary
Table 16-9.
8210B–AVR–04/10
Address
Address
Address
+0x00
+0x01
+0x08
+0x00
+0x01
+0x02
+0x03
+0x04
+0x05
+0x06
+0x00
+0x01
+0x02
+0x03
+0x04
+0x05
Offset
0x00
0x02
Name
Name
Name
ADDRMASK
MASTER
STATUS
STATUS
CTRLC
SLAVE
CTRLA
CTRLB
CTRLA
CTRLB
TWI Interrupt vectors and their word offset addresses
BAUD
ADDR
ADDR
CTRL
DATA
DATA
MASTER_vect
SLAVE_vect
Bit 7
Bit 7
Bit 7
RIF
DIF
Source
–
–
–
–
INTLVL[1:0]
INTLVL[1:0]
Bit 6
Bit 6
Bit 6
APIF
WIF
–
–
–
–
Interrupt Description
TWI Master Interrupt vector
TWI Slave Interrupt vector
CLKHOLD
CLKHOLD
Bit 5
Bit 5
Bit 5
RIEN
DIEN
–
–
–
–
ADDRMASK[7:1]
Offset address for TWI Master
Offset address for TWI Slave
RXACK
RXACK
Bit 4
Bit 4
Bit 4
APIEN
WIEN
–
–
–
–
ADDR[7:0]
ADDR[7:0]
BAUD[7:0]
DATA[7:0]
DATA[7:0]
ARBLOST
ENABLE
ENABLE
Bit 3
Bit 3
Bit 3
COLL
–
–
–
TIMEOUT[1:0]
BUSERR
BUSERR
ACKACT
ACKACT
Bit 2
Bit 2
Bit 2
PIEN
–
–
SDAHOLD
TPMEN
Bit 1
Bit 1
Bit 1
QCEN
DIR
–
BUSSTATE[1:0]
CMD[1:0]
CMD[1:0]
ADDREN
XMEGA D
Bit 0
EDIEN
Bit 0
SMEN
Bit 0
SMEN
AP
–
Page
Page
Page
181
181
182
183
184
185
186
186
187
187
188
190
190
191
192