ATxmega128D3 Atmel Corporation, ATxmega128D3 Datasheet - Page 28

• Manufacturer Part Number: ATxmega128D3
• Manufacturer: Atmel Corporation

Specifications of ATxmega128D3

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 200
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 18
• Input Capture Channels: 18
• Pwm Channels: 18
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

4.13
4.13.1
4.13.2
8210B–AVR–04/10
Register Description – Fuses and Lockbit
FUSEBYTE1 - Non-Volatile Memory Fuse Byte1 - Watchdog Configuration
FUSEBYTE2 - Non-Volatile Memory Fuse Byte2 - Reset Configuration
• Bit 7:4 - WDWPER[3:0]: Watchdog Window Timeout Period
The WDWPER fuse bits are used to set initial value of the closed window for the Watchdog
Timer in Window Mode. During reset these fuse bits are automatically written to the WPER bits
Watchdog Window Mode Control Register, refer to
Control Register” on page 120
• BIT 3:0 - WDPER[3:0]: Watchdog Timeout Period
The WDPER fuse bits are used to set initial value of the Watchdog Timeout Period. During reset
these fuse bits are automatically written to the PER bits in the Watchdog Control Register, refer
to
• Bit 7 - Reserved
This fuse bit is reserved. For compatibility with future devices, always write this bit to one when
this register is written.
• Bit 6 - BOOTRST: Boot Loader Section Reset Vector
The BOOTRST fuse can be programmed so the Reset Vector is pointing to the first address in
the Boot Loader Flash Section. In this case, the device will start executing from the from Boot
Loader Flash Section after reset.
Table 4-1.
• Bit 5:2 - Reserved
These fuse bits are reserved. For compatibility with future devices, always write these bits to one
when this register is written.
Bit
+0x02
Read/Write
Initial Value
Bit
+0x01
Read/Write
Initial Value
Section 11.7.1 ”CTRL – Watchdog Timer Control Register” on page 119
BOOTRST
0
1
Boot Reset Fuse
R/W
Reset Address
Reset Vector = Boot Loader Reset
Reset Vector = Application Reset (address 0x0000)
7
0
R
7
–
1
R/W
WDWPER[3:0]
6
0
BOOTRST
R/W
6
1
for details.
R/W
5
0
R
5
–
1
R/W
4
0
R
4
–
1
R/W
3
0
Section 11.7.2 ”WINCTRL – Window Mode
R
3
–
1
R/W
2
0
WDPER[3:0]
R
2
–
1
R/W
1
0
R/W
1
1
BODPD[1:0]
R/W
for details.
0
0
XMEGA D
R/W
0
1
FUSEBYTE1
FUSEBYTE2
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