ATxmega128D3 Atmel Corporation, ATxmega128D3 Datasheet - Page 232

• Manufacturer Part Number: ATxmega128D3
• Manufacturer: Atmel Corporation

Specifications of ATxmega128D3

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 200
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 18
• Input Capture Channels: 18
• Pwm Channels: 18
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.8.2
8210B–AVR–04/10
Single conversion with gain
The analog input source is sampled in the first half of the first cycle, and the sample time is one-
half ADC clock period. Using a faster or slower ADC clock and sample rate will affect the sample
time.
The Most Significant Bit (MSB) of the result is converted first, and the rest of the bits are con-
verted during the next 3 (for 8-bit results) or 5 (for 12-bit results) ADC clock cycles. Converting
one bit takes a half ADC clock period. During the last cycle the result is prepared before the
Interrupt Flag is set. The result is available in the Result Register for readout.
Figure 20-13. ADC timing for one single conversion without gain
Figure 20-14 on page 232
version with various gain settings. As seen in the
placed prior to the actual ADC. This means that the gainstage will sample and amplify the ana-
log input source before the ADC samples an converts the amplified analog value.
The gain stage will require between one and three ADC clock cycles in order to amplify the input
source. This will add one to three ADC clock cycles to the total propagation delay compared to
single conversion without gain. The sample time for the gain stage is a half ADC clock cycle.
Figure 20-14. ADC timing for one single conversion with 2x or 4x gain
GAINSTAGE AMPLIFY
GAINSTAGE SAMPLE
CONVERTING BIT
CONVERTING BIT
ADC SAMPLE
ADC SAMPLE
CLK
START
CLK
START
ADC
ADC
IF
IF
1
1
MSB
to
10
Figure 20-16 on page
2
MSB
2
9
10
3
8
9
3
7
8
4
6
7
4
233show the ADC timing for one single con-
”Overview” on page 224
5
6
5
4
5
5
4
3
6
3
2
6
2
1
7
1
LSB
XMEGA D
LSB
the gain stage is
7
8
8
9
232