ATxmega128D3 Atmel Corporation, ATxmega128D3 Datasheet - Page 24

• Manufacturer Part Number: ATxmega128D3
• Manufacturer: Atmel Corporation

Specifications of ATxmega128D3

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 200
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 18
• Input Capture Channels: 18
• Pwm Channels: 18
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

4.12.6
4.12.7
4.12.8
8210B–AVR–04/10
DATA0 - Non-Volatile Memory Data Register 0
CMD - Non-Volatile Memory Command Register
CTRLA - Non-Volatile Memory Control Register A
• Bit 7:0 - DATA[7:0]: NVM Data Register Byte 0
This register gives the data value byte 0 when accessing either of the memory locations.
• Bit 7 - Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bit 6:0 -CMD[6:0]: NVM Command
These bits define the programming commands for the flash. Bit six is set for external program-
ming commands. See "Memory Programming datasheet" for programming commands.
• Bit 7:1 - Reserved Bits
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 0 - CMDEX: Non-Volatile Memory Command Execute
Writing this bit to one will execute the command in the CMD register. This bit is protected by the
Configuration Change Protection (CCP) mechanism, refer to
Change Protection” on page 12
Bit
+0x04
Read/Write
Initial Value
Bit
+0x0A
Read/Write
Initial Value
Bit
+0x0B
Read/Write
Initial Value
R/W
R
R
7
0
7
–
0
7
–
0
R/W
R/W
R
6
0
6
0
6
–
0
for details on the CCP.
R/W
R/W
R
5
0
5
0
5
–
0
R/W
R/W
R
4
0
4
0
4
–
0
DATA[7:0]
CMD[6:0]
R/W
R/W
R
3
0
3
0
3
–
0
R/W
R/W
R
2
0
2
0
2
–
0
Section 3.12 ”Configuration
R/W
R/W
R
1
0
1
0
1
–
0
XMEGA D
CMDEX
R/W
R/W
S
0
0
0
0
0
0
CTRLA
DATA0
CMD
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