M40800 Atmel Corporation, M40800 Datasheet - Page 243
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
M40800
Manufacturer Part Number
M40800
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(21 pages)
3.M40800.pdf
(18 pages)
4.M40800.pdf
(153 pages)
Specifications of M40800
Flash (kbytes)
0 Kbytes
Pin Count
100
Max. Operating Frequency
40 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
No
Calibrated Rc Oscillator
No
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ARM DDI 0029G
The instruction in Example B-1 on page B-24 causes the contents of the registers to
appear on the data bus. You can then sample and shift out these values.
The use of
any register.
After you have determined the values in the current bank of registers, you might want
to access the banked registers. To do this, you must change mode. Typically, a mode
change can occur only if the core is already in a privileged mode. However, while in
debug state, a mode change from one mode into any other mode can occur. The
debugger must restore the original mode before exiting debug state.
For example, if the debugger has been requested to return the state of the User mode
registers and FIQ mode registers and debug state was entered in Supervisor mode, the
instruction sequence can be as listed in Example B-2.
All these instructions execute at debug speed. Debug speed is much slower than system
speed. This is because between each core clock, 33 clocks occur in order to shift in an
instruction, or shift out data. Executing instructions this slowly is acceptable for
accessing the core state because the ARM7TDMI core is fully static. However, you
cannot use this method for determining the state of the rest of the system.
While in debug state, only the following instructions can be scanned into the instruction
pipeline for execution:
•
•
•
all data processing operations
all load, store, load multiple, and store multiple instructions
MSR and MRS.
Note
Copyright © 1994-2001. All rights reserved.
as the base register for the STM is only for illustration and you can use
Example B-2 Determining state of User and FIQ mode registers
Debug in Depth
B-25
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