M40800 Atmel Corporation, M40800 Datasheet - Page 83
M40800
Manufacturer Part Number
M40800
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(21 pages)
3.M40800.pdf
(18 pages)
4.M40800.pdf
(153 pages)
Specifications of M40800
Flash (kbytes)
0 Kbytes
Pin Count
100
Max. Operating Frequency
40 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
No
Calibrated Rc Oscillator
No
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3.4.5
3.4.6
3.4.7
ARM DDI 0029G
nTRANS
LOCK
TBIT
The nTRANS output conveys information about the transfer. A MMU can use this
signal to determine whether an access is from a privileged mode or User mode. This
signal can be used with nOPC to implement an access permission scheme. The
meaning of nTRANS is listed in Table 3-5.
More information relevant to the nTRANS signal and security is provided in Privileged
mode access on page 3-32.
LOCK is used to indicate to an arbiter that an atomic operation is being performed on
the bus. LOCK is normally LOW, but is set HIGH to indicate that a SWP or SWPB
instruction is being performed. These instructions perform an atomic read/write
operation, and can be used to implement semaphores.
TBIT is used to indicate the operating state of the ARM7TDMI processor. When in:
•
•
Memory systems do not usually have to use TBIT because MAS[1:0] indicates the size
of the instruction required.
ARM state, the TBIT signal is LOW
Thumb state, the TBIT signal is HIGH.
Note
Copyright © 1994-2001. All rights reserved.
nTRANS
0
1
Table 3-5 nTRANS encoding
Mode
User
Privileged
Memory Interface
3-13
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