M40800 Atmel Corporation, M40800 Datasheet - Page 87
M40800
Manufacturer Part Number
M40800
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(21 pages)
3.M40800.pdf
(18 pages)
4.M40800.pdf
(153 pages)
Specifications of M40800
Flash (kbytes)
0 Kbytes
Pin Count
100
Max. Operating Frequency
40 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
No
Calibrated Rc Oscillator
No
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3.6
3.6.1
ARM DDI 0029G
Data timed signals
D[31:0], DOUT[31:0], and DIN[31:0]
This section describes:
•
•
•
•
The ARM7TDMI processor provides both unidirectional data buses, DIN[31:0],
DOUT[31:0], and a bidirectional data bus, D[31:0]. The configuration input BUSEN is
used to select which is active. Figure 3-11 shows the arrangement of the data buses and
bus-splitter logic.
When the bidirectional data bus is being used then you must disable the unidirectional
buses by driving BUSEN LOW. The timing of the bus for three cycles, load-store-load,
is shown in Figure 3-12 on page 3-18.
D[31:0], DOUT[31:0], and DIN[31:0] on page 3-17
ABORT on page 3-24
Byte latch enables on page 3-24
Byte and halfword accesses on page 3-26.
Copyright © 1994-2001. All rights reserved.
ARM7TDMI
Latch control
EmbeddICE
Buffer control
Logic
Figure 3-11 External bus arrangement
Latch
G
Memory Interface
DIN[31:0]
DOUT[31:0]
D[31:0]
3-17
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