M42800A Atmel Corporation, M42800A Datasheet - Page 131

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

TC User Interface
TC Base Address: 0xFFFE0000 (Code Label TC_BASE)
Table 16. TC Global Memory Map
TC_BCR (Block Control Register) and TC_BMR (Block Mode Register) control the TC block. TC Channels are controlled
by the registers listed in Table 17. The offset of each of the Channel registers in Table 17 is in relation to the offset of the
corresponding channel as mentioned in Table 16.
Table 17. TC Channel Memory Map
Note:
1354D–ATARM–08/02
Offset
Offset
0xC0
0xC4
0x0C
0x1C
0x2C
0x00
0x40
0x80
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
Read Only if WAVE = 0
Channel/Register
TC Channel 0
TC Channel 1
TC Channel 2
TC Block Control Register
TC Block Mode Register
Register
Channel Control Register
Channel Mode Register
Reserved
Reserved
Counter Value
Register A
Register B
Register C
Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
TC_BMR
TC_CCR
TC_CMR
TC_BCR
TC_IMR
TC_IER
TC_IDR
TC_CV
TC_RA
TC_RB
TC_RC
TC_SR
Name
Name
See Table 17
See Table 17
See Table 17
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read Only
Read Only
Write Only
Write Only
Write Only
Write Only
Access
Access
AT91X40 Series
(1)
(1)
Reset State
Reset State
–
0
–
0
–
–
0
0
0
0
0
–
–
0
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