M42800A Atmel Corporation, M42800A Datasheet
M42800A
Specifications of M42800A
Related parts for M42800A
M42800A Summary of contents
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... Core and PLL Operating Voltage Range; 2.7V to 5.5V I/O Operating Voltage Range • - +85 C Temperature Range • Available in a 144-lead LQFP Package (Green) and a 144-ball BGA Package (RoHS compliant) ® Processor Core DDCORE AT91 ARM Thumb Microcontrollers AT91M42800A = 3.0V, Rev. 1779D–ATARM–14-Apr-06 ...
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... Description The AT91M42800A is a member of the Atmel AT91 16/32-bit microcontroller family, which is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addi- tion, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The AT91 ARM-based MCU family also features Atmel’ ...
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... Pin Configuration Figure 2-1. Pin Configuration in TQFP144 Package (Top View) Figure 2-2. Pin Configuration in BGA144 Package (Top View 1779D–ATARM–14-Apr-06 108 73 109 AT91M42800 33AI 144 AT91M42800A ...
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... Table 1. AT91M42800A Pinout in TQFP 144 Package Pin# Name Pin# 1 GND 37 2 GND 38 3 NLB/ VDDIO 48 13 GND A10 51 16 A11 52 17 A12 53 18 A13 54 19 A14 ...
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... Table 2. AT91M42800A Pinout in BGA 144 Package Pin# Name A1 PB1/NCS3 A2 NCS0 A3 NCS1 A4 GND A5 PLLRCB A6 GND A7 PLLRCA A8 GND A9 XOUT A10 XIN A11 MODE0 A12 PA22/NPCSB1 B1 NUB/NWR1 B2 PB0/NCS2 B3 VDDCORE B4 NWE/NWR0 B5 VDDPLL B6 TDO B7 VDDPLL B8 NWDOVF B9 PA26 B10 PA19/MISOB B11 PA24/NPCSB3 B12 PA23/NPCSB2 C1 NLB/ VDDIO ...
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... Pin Description Table 3. AT91M42800A Pin Description Module Name A0 - A23 D0 - D15 CS4 - CS7 NCS0 - NCS3 NWR0 NWR1 NRD EBI NWE NOE NUB NLB NWAIT BMS PME IRQ0 - IRQ3 AIC FIQ TCLK0 - TCLK5 TC TIOA0 - TIOA5 TIOB0 - TIOB5 SCK0 - SCK1 USART TXD0 - TXD1 RXD0 - RXD1 ...
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... Table 3. AT91M42800A Pin Description (Continued) Module Name XIN XOUT CLOCK PLLRCA PLLRCB MCKO NRST Test and Reset MODE0 - MODE1 TMS TDI JTAG/ICE TDO TCK NTRST Emulation NTRI VDDIO VDDCORE Power VDDPLL GND 1779D–ATARM–14-Apr-06 Function Oscillator Input or External Clock ...
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... PA9/TXD1/NTRI PA10/RXD1 P I PA11/SPCKA O PA12/MISOA PA13/MOSIA PA14/NPCSA0/NSSA PA15/NPCSA1 PA16/NPCSA2 PA17/NPCSA3 PA18/SPCKB PA19/MISOB PA20/MOSIB PA21/NPCSB0/NSSB PA22/NPCSB1 PA23/NPCSB2 PA24/NPCSB3 AT91M42800A 8 Embedded ICE ARM7TDMI Core ASB Internal RAM 8K Bytes ASB Controller AMBA™ Bridge AIC: Advanced Interrupt Controller 2 PDC USART0 Channels APB 2 PDC USART1 ...
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... Memories The AT91M42800A microcontroller embeds bytes of internal SRAM. The internal memory is directly connected to the 32-bit data bus and is single-cycle accessible. This pro- vides maximum performance of 30 MIPS at 33 MHz by using the ARM instruction set of the processor. The on-chip memory significantly reduces the system power consumption and improves its performance over external memory solutions ...
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... Each TC also has three external clock signals. Two independently configurable SPIs provide communication with external devices in master or slave mode. Each has four external chip selects which can be connected devices. The data length is programmable, from 8- to 16-bit. AT91M42800A 10 1779D–ATARM–14-Apr-06 ...
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... Input/Output Considerations After the reset, the peripheral I/Os are initialized as inputs to provide the user with maximum flexibility recommended that in any application phase, the inputs to the AT91M42800A microcontroller be held at valid logic levels to minimize the power consumption. 1779D–ATARM–14-Apr-06 Document Title ...
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... Except for the program counter, the ARM core registers do not have defined reset states. When reset is active, the inputs of the AT91M42800A must be held at valid logic levels. The EBI address lines drive low during reset. All the peripheral clocks are disabled dur- ing reset to save power ...
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... Emulation Functions 7.6.1 Tri-state Mode The AT91M42800A provides a Tri-state mode, which is used for debug purposes in order to connect an emulator probe to an application board. In Tri-state mode the AT91M42800A con- tinues to function, but all the output pin drivers are tri-stated. To enter Tri-state mode, the pin NTRI must be held low during the last 10 SLCK clock cycles before the rising edge of NRST ...
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... Internal Memories The AT91M42800A microcontroller integrates an 8-Kbyte primary internal SRAM. All internal memories are 32 bits wide and single-clock cycle accessible. Byte (8-bit), half-word (16-bit) or word (32-bit) accesses are supported and are executed within one cycle. Fetching Thumb or ARM instructions is supported and internal memory can store twice as many Thumb instruc- tions as ARM ones ...
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... The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt, Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors to be redefined dynamically by the software, the AT91M42800A microcontroller uses a remap command that enables switching between the boot memory and the internal SRAM bank addresses ...
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... Peripherals The AT91M42800A peripherals are connected to the 32-bit wide Advanced Peripheral Bus. Peripheral registers are only word accessible. Byte and half-word accesses are not supported byte or a half-word access is attempted, the memory controller automatically masks the lowest address bits and generates a word access ...
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... Peripheral Data Controller The AT91M42800A has an 8-channel PDC dedicated to the two on-chip USARTs and to the two on-chip SPIs. One PDC channel is connected to the receiving channel and one to the transmitting channel of each peripheral. The user interface of a PDC channel is integrated in the memory space of each USART chan- nel and in the memory space of each SPI ...
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... PIO: Parallel I/O Controller The AT91M42800A has 54 programmable I/O lines. I/O lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins. These lines are controlled by two separate and identical PIO Controllers called PIOA and PIOB. Each PIO controller also provides an internal interrupt signal to the Advanced Interrupt Controller and insertion of a sim- ple input glitch filter on any of the PIO pins ...
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... SPI: Serial Peripheral Interface The AT91M42800A includes two SPIs that provide communication with external devices in Master or Slave mode. They are independent, and are referred to by the letters A and B. Each SPI has four external chip selects that can be connected devices. The data length is programmable from 8- to 16-bit. 1779D– ...
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... Memory Map Figure 9-1. AT91M42800A Memory Map before Remap Command Address 0xFFFFFFFF 0xFFC00000 0xFFBFFFFF 0x00400000 0x003FFFFF 0x00300000 0x002FFFFF 0x00200000 0x001FFFFF 0x00100000 0x000FFFFF 0x00000000 Note: AT91M42800A 20 Function Size Protection On-chip 4M Bytes Privileged Peripherals Reserved On-chip SRAM 1M Byte Reserved 1M Byte On-chip Device Reserved 1M Byte ...
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... Figure 9-2. AT91M42800A Memory Map after Remap Command Address 0xFFFFFFFF 0xFFC00000 0xFFBFFFFF 0x00400000 0x003FFFFF 0x00300000 0x002FFFFF 0x00200000 0x001FFFFF 0x00100000 0x000FFFFF 0x00000000 Note: 1779D–ATARM–14-Apr-06 Function Size 4M Bytes On-chip Peripherals External Devices Devices Programmable Page Size ( 16, 64M Bytes ...
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... Peripheral Memory Map Figure 10-1. AT91M42800A Peripheral Memory Map Address 0xFFFFFFFF 0xFFFFF000 0xFFFFEFFF 0xFFFFC000 0xFFFFBFFF 0xFFFF8000 0xFFFF7FFF 0xFFFF4000 0xFFFF3FFF 0xFFFF0000 0xFFFEFFFF 0xFFFEC000 0xFFFEBFFF 0xFFFD8000 0xFFFD7FFF 0xFFFD4000 0xFFFD3FFF 0xFFFD0000 0xFFFCFFFF 0xFFFCC000 0xFFFCBFFF 0xFFFC8000 0xFFFC7FFF 0xFFFC4000 0xFFFC3FFF 0xFFFC0000 0xFFFBFFFF 0xFFF04000 0xFFF03FFF 0xFFF00000 0xFFEFFFFF 0xFFF04000 ...
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... NCS lines. The Chip Select Register, having the smaller number, defines the characteristics of the external access and the behaviour of the control signals. 1779D–ATARM–14-Apr-06 48). Note that A0 - A23 is only significant for 8-bit memory A23 is used for 16-bit Figure 11-1 on page AT91M42800A Section 11.13 ”EBI User Interface” on 24). 23 ...
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... When the ARM core performs accesses in the internal memories or the embedded peripher- als, the EBI signals behave as follows: • The address lines remain at the level of the last external access. • The data bus is tri-stated. • The control signals remain in an inactive state. AT91M42800A Byte Device Low ...
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... Upper and lower byte select Wait request Protection Mode Enabled Functions Allows from chip select lines to be used 8- or 16-bit data bus Byte-write or byte select access Byte-write or byte select access Byte-write or byte select access AT91M42800A Type Output I/O Output Output Output Output Output ...
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... Data Bus Width A data bus width bits can be selected for each chip select. This option is controlled by the DBW field in the EBI_CSR (Chip Select Register) for the corresponding chip select. Figure 11-4 shows how to connect a 512K x 8-bit memory on NCS2. AT91M42800A 26 (1) NCS0 ...
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... D15 A1 - A18 EBI A0 NWR1 NWR0 NRD NCS2 D15 A1 - A19 EBI NLB NUB NWE NOE NCS2 AT91M42800A A18 A0 Write Enable Output Enable Memory Enable D15 A0 - A18 Low Byte Enable High Byte Enable Write Enable Output Enable Memory Enable 27 ...
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... Figure 11-7 shows how to connect a 16-bit device with byte and half-word access (e.g., 16-bit SRAM) on NCS2. Figure 11-7. Connection for a 16-bit Data Bus with Byte and Half-word Access Figure 11-8 shows how to connect a 16-bit device without byte access (e.g., Flash) on NCS2. AT91M42800A D15 A1 - A19 ...
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... D15 A1 - A19 EBI NLB NUB NWE NOE NCS2 in ns) CE Values take only t into account. CE AT91M42800A D15 A0 - A18 Write Enable Output Enable Memory Enable ”Operating Modes” on page 12, External Oscillator Frequency Limit (MHz ...
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... However, an extra wait state is required in some cases to avoid contentions on the external bus. AT91M42800A 30 In the following waveforms and descriptions, NRD represents NRD and NOE since the two sig- nals have the same waveform ...
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... NWE waveform (on the NWE pin) is used to control the output data timing to guaran- tee this operation. 1779D–ATARM–14-Apr-06 MCKI ADDR NCS NRD or NWE Figure 11-11). This wait state is generated in addition to any other pro- Write Cycle Early Read Wait MCKI ADDR NCS NRD NWE AT91M42800A Read Cycle Figure 11-12. The 31 ...
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... Below is the correspondence between the number of standard wait states programmed and the number of cycles during which the NWE pulse is held low: 0 wait states 1 wait state For each additional wait state programmed, an additional cycle is added. AT91M42800A 32 MCKI ADDR NWE Data Output ” ...
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... Wait State Access MCKI ADDR NCS NWE NRD (2) (1) 1. Early Read Protocol 2. Standard Read Protocol ) for each external memory device is programmed in the TDF DF will not slow down the execution of a program from internal DF AT91M42800A 33 ...
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... When NWAIT is de-asserted, the EBI fin- ishes the access sequence. The NWAIT signal must meet setup and hold requirements on the rising edge of the clock. Figure 11-15. External Wait Notes: AT91M42800A 34 MCKI ADDR NCS ...
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... If any wait states have already been inserted, (e.g., data float wait) then none are added. Figure 11-16. Chip Select Wait Notes: 1779D–ATARM–14-Apr-06 Mem 1 MCKI NCS1 NCS2 NRD (1) (2) NWE 1. Early Read Protocol 2. Standard Read Protocol AT91M42800A Chip Select Wait Mem 2 35 ...
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... Memory Access Waveforms Figures 11-17 through 11-20 show examples of the two alternative protocols for external memory read access. Figure 11-17. Standard Read Protocol without t AT91M42800A 36 DF 1779D–ATARM–14-Apr-06 ...
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Write Read Early Read Mem 1 Mem 1 Wait Cycle MCKI A0 - A23 NRD NWE NCS1 NCS2 D0 - D15 (Mem D15 (AT91 D15 (Mem 2) Read Read Write Early Read Mem 1 Mem ...
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Write Mem 1 Read Mem 1 Data Float Wait MCKI A0 - A23 NRD NWE NCS1 NCS2 D15 (Mem D15 (AT91 (Mem 2) Read Mem 2 Read Mem 1 Read ...
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Write Mem 1 Read Mem 1 Data Float Wait MCKI A0 - A23 NRD NWE NCS1 NCS2 D15 (Mem D15 (AT91 D15 (Mem 2) Early Read Read Wait Mem 2 Read ...
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... Figures 11-21 through 11-27 show the timing cycles and wait states for read and write access to the various AT91M42800A external memory devices. The configurations described are shown in the following table: Table 11-3. Figure Number AT91M42800A 40 Memory Access Waveforms Number of Wait States 11-21 0 11-22 1 11-23 1 11-24 0 11-25 1 11-26 1 11-27 0 ...
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... Early Protocol NRD D0 - D15 WRITE ACCESS · Byte Write/ Byte Select Option NWE D0 - D15 1779D–ATARM–14-Apr-06 ADDR ADDR AT91M42800A ...
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... NLB NUB READ ACCESS · Standard Protocol NRD D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS · Byte Write/ Byte Select Option NWE D0 - D15 AT91M42800A 42 1 Wait State ADDR Wait State ...
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... Standard Protocol D0 - D15 Internal Bus · Early Protocol D0 - D15 WRITE ACCESS · Byte Write/ Byte Select Option NWE D0 - D15 1779D–ATARM–14-Apr-06 1 Wait State NCS NLB NUB NRD NRD AT91M42800A ...
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... Figure 11-24. 0 Wait States, 8-bit Bus Width, Word Transfer MCKI ADDR A0 - A23 NCS READ ACCESS · Standard Protocol NRD D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS NWR0 NWR1 D0 - D15 AT91M42800A 44 ADDR+1 ADDR ...
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... Standard Protocol NRD D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS NWR0 NWR1 D0 - D15 1779D–ATARM–14-Apr-06 1 Wait State ADDR AT91M42800A ADDR ...
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... Figure 11-26. 1 Wait State, 8-bit Bus Width, Byte Transfer MCKI A0 - A23 NCS READ ACCESS · Standard Protocol NRD D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS NWR0 NWR1 D0 - D15 AT91M42800A 46 1 Wait State 1779D–ATARM–14-Apr-06 ...
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... Byte Write Option NWR0 NWR1 D0 - D15 · Byte Select Option NWE 1779D–ATARM–14-Apr-06 ADDR ADDR AT91M42800A ADDR ADDR ...
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... Notes: AT91M42800A 48 EBI Memory Map Register Chip Select Register 0 EBI_CSR0 Chip Select Register 1 EBI_CSR1 Chip Select Register 2 EBI_CSR2 Chip Select Register 3 EBI_CSR3 Chip Select Register 4 EBI_CSR4 Chip Select Register 5 ...
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... BAT WSE NWS Data Bus Width Reserved 16-bit data bus width 8-bit data bus width Reserved Number of Standard Wait States AT91M42800A – – – TDF PAGES DBW Code Label: EBI_DBW – ...
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... Chip select is enabled. • BA: Base Address (Code Label EBI_BA) These bits contain the highest bits of the base address. If the page size is larger than 1M byte, the unused bits of the base address are ignored by the EBI decoder. AT91M42800A 50 Active Bits in Base Address 12 Bits (31 - 20) ...
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... Cancels the remapping (performed at reset) of the page zero memory devices. 1779D–ATARM–14-Apr- – – – – – – – – – – – – AT91M42800A – – – – – – – – – – – RCB 51 ...
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... A20 None • DRP: Data Read Protocol DRP Selected DRP 0 Standard read protocol for all external memory devices enabled 1 Early read protocol for all external memory devices enabled AT91M42800A – – – – – – – ...
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... PDC ARM – – – AT91M42800A 26 25 – – – – ABTTYP ABTSZ 2 1 – MISADD Abort Size Byte Half-word Word Reserved Abort Size Data read Data write Code fetch ...
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... Abort Address Status Register Register Name: EBI_AASR Access Type: Read-only Offset: 0x34 Reset Value: 0x0 • ABTADD: Abort Address This field contains the address required by the last aborted access. AT91M42800A ABTADD ABTADD ABTADD ABTADD 26 ...
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... PMC: Power Management Controller The AT91M42800A’s Power Management Controller optimizes the power consumption of the device. The PMC controls the clocking elements such as the oscillator and the PLLs, and the System and the Peripheral Clocks. It also controls the MCKO pin and enables the user to select four different signals to be driven on this pin ...
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... Note: 12.2.1 Phase Locked Loops Two PLLs are integrated in the AT91M42800A in order to cover a larger frequency range. Both PLLs have a Slow Clock input and a dedicated pin (PLLRCA or PLLRCB), which must have appropriate capacitors and resistors. The capacitors and resistors serve as a second AT91M42800A ...
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... Clock cycles plus 2.5 PLL output signal cycles. This is a maximum value. 1779D–ATARM–14-Apr-06 PLLRC GND PLLA 32.768 kHz SCLK F _PLLA = 16.776 MHz out R = 1600 Ohm C = 100 PLLB 32.768 kHz SCLK F _PLLB = 33.554 MHz out R = 800 Ohm µ 100 nF 2 AT91M42800A PLL 57 ...
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... PLL Lock Timer The Power Management Controller of the AT91M42800A integrates a dedicated 8-bit timer for the locking time of the PLL. This timer is loaded with the value written in PLLCOUNT each time the value in the field MUL changes. At the same time, the LOCK bit in PMC_SR is cleared, and the PLL is bypassed ...
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... ARM Processor Clock Controller The AT91M42800A has only one System Clock. It can be enabled and disabled by writing the System Clock Enable (PMC_SCER) and System Clock Disable Registers (PMC_SCDR). The status of this clock (at least for debug purpose) can be read in the System Clock Status Regis- ter (PMC_SCSR) ...
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... This is to avoid data corruption or erroneous behavior of the system. Note: Figure 12-8. Peripheral Clock Control AT91M42800A 60 The bits defined to control the Peripheral Clocks correspond to the bits controlling the Interrupt Sources in the Interrupt Controller. ...
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... Reserved 0x28 Reserved 0x2C Reserved 0x30 Status Register 0x34 Interrupt Enable Register 0x38 Interrupt Disable Register 0x3C Interrupt Mask Register 1779D–ATARM–14-Apr-06 AT91M42800A Register Mnemonic Access PMC_SCER Write-only PMC_SCDR Write-only PMC_SCSR Read-only – – PMC_PCER Write-only PMC_PCDR Write-only ...
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... Write-only Offset: 0x00 31 30 – – – – – – – – • CPU: System Clock Enable effect Enables the System Clock. AT91M42800A – – – – – – – – – – ...
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... AT91M42800A – – – – – – – – – – – CPU – – – ...
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... Write-only Offset: 0x14 31 30 – – – – – PIOB 7 6 TC1 TC0 • Peripheral Clock Disable effect Disables the peripheral clock. AT91M42800A – – –– – – – PIOA – TC5 ...
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... Peripheral clock is disabled Peripheral clock is enabled. 1779D–ATARM–14-Apr- – – – – – – PIOA – TC5 SPIB SPIA US1 AT91M42800A – – – – – – TC4 TC3 TC2 US0 – – 65 ...
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... Master Clock 1 0 Master Clock inverted 1 1 Master Clock divided by 2 • MCKODS: Master Clock Output Disable (Code Label PMC_MCKO_DIS The pin MCKO is driven with the clock selected by MCKOSS The pin MCKO is tri-stated. AT91M42800A PLLCOUNT – – – ...
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... The PLL output is at frequency (MUL+1) x Slow Clock frequency when the LOCK bit is set. • PLLCOUNT: PLL Lock Counter Specifies the number of 32,768 Hz clock cycles for the PLL lock timer to count before the PLL is locked, after the PLL is started. 1779D–ATARM–14-Apr-06 AT91M42800A 67 ...
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... LOCK: PLL Lock Status 0 = The PLL output signal is not stabilized The PLL output signal is stabilized. AT91M42800A – – – – – – – – ...
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... AT91M42800A – – – – – – – – – – – LOCK – – – ...
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... LOCK: PLL Lock Interrupt Mask 0 = The PLL Lock Interrupt is disabled The PLL Lock Interrupt is enabled. AT91M42800A – – – – – – – – ...
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... APB Interface Down Counter SLCK Slow Clock If ST_PIMR is programmed with a period less or equal to the current MCK period, the update of the PITS status bit and its associated interrupt generation are unpredictable. AT91M42800A STIRQ System Timer Interrupt NWDOVF PIV Period Interval Value 16-bit ...
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... The bit RTTINC in ST_SR is set each time the 20-bit counter is incremented. This bit can be used to start an interrupt, or generate a one-second signal. Writing the ST_RTMR immediately reloads and restarts the clock divider with the new pro- grammed value. This also resets the 20-bit counter. AT91M42800A 72 16-bit Down 1/128 ...
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... Real Time Prescalar 16-bit Divider SLCK Slow Clock If RTPRES is programmed with a period less or equal to the current MCK period, the update of the RTTINC and ALMS status bits and their associated interrupt generation are unpredictable. AT91M42800A RTTINC Real-time Timer Increment 20-bit Counter = ALMS ...
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... WDRST: Watchdog Timer Restart effect Reload the start-up value in the Watchdog Timer. AT91M42800A 74 Register Mnemonic ST_CR ST_PIMR ST_WDMR ST_RTMR ST_SR ST_IER ST_IDR ST_IMR ST_RTAR ST_CRTR – – ...
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... PIV PIV – – – – – – WDV WDV AT91M42800A – – – – – – – – – – EXTEN RSTEN ...
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... The Real-time Timer has been incremented since the last read of the Status Register. • ALMS: Alarm Status alarm compare has been detected since the last read of the Status Register Alarm compare has been detected since the last read of the Status Register. AT91M42800A – ...
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... Enables the Alarm Status Interrupt. 1779D–ATARM–14-Apr- – – – – – – – – – – – ALMS AT91M42800A – – – – – – – – – RTTINC WDOVF PITS 77 ...
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... No effect Disables the Watchdog Overflow Interrupt. • RTTINC: Real-time Timer Increment Interrupt Disable effect Disables the Real-time Timer Increment Interrupt. • ALMS: Alarm Status Interrupt Disable effect Disables the Alarm Status Interrupt. AT91M42800A – – – ...
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... Alarm Status Interrupt is enabled. 1779D–ATARM–14-Apr- – – – – – – – – – – – ALMS AT91M42800A – – – – – – – – – RTTINC WDOVF PITS 79 ...
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... Register Name: ST_CRTR Access Type: Read-only Offset: 0x24 Reset Value: 0x0 31 30 – – • CRTV: Current Real-time Value Returns the current value of the Real-time Timer. AT91M42800A – – – ALMV ALMV ALMV ...
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... AIC: Advanced Interrupt Controller The AT91M42800A has an 8-level priority, individually maskable, vectored interrupt controller. This feature substantially reduces the software and real-time overhead in handling internal and external interrupts. The interrupt controller is connected to the NFIQ (fast interrupt request) and the NIRQ (stan- dard interrupt request) inputs of the ARM7TDMI processor. The processor’ ...
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... Hardware Interrupt Vectoring The hardware interrupt vectoring reduces the number of instructions to reach the interrupt handler to only one. By storing the following instruction at address 0x00000018, the processor AT91M42800A 82 Interrupt Description FIQ Fast Interrupt SW Soft Interrupt (generated by the AIC) US0 USART Channel 0 interrupt ...
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... Each interrupt source, including FIQ, can be enabled or disabled using the command registers AIC_IECR and AIC_IDCR. The interrupt mask can be read in the Read-only register AIC_IMR. A disabled interrupt does not affect the servicing of other interrupts. 1779D–ATARM–14-Apr-06 ldr PC,[PC,# -&F20] Table AT91M42800A 14-1) is serviced first. 83 ...
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... Once the AIC enters the spurious interrupt management, it asserts neither the NIRQ nor the NFIQ lines to the ARM7TDMI as long as the spurious interrupt is not acknowledged. There- fore mandatory for the Spurious Interrupt Service Routine to acknowledge the “spurious” AT91M42800A 84 ldr PC,[PC,# -&F20] ...
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... Software that has been written and debugged using Protect mode will run correctly in Nor- mal mode without modification. However, in Normal mode, the AIC_IVR write has no effect and can be removed to optimize the code. AT91M42800A Normal Mode Protect Mode Read AIC_IVR Read AIC_IVR ...
Page 86
... Interrupt Enable Command Register 0x124 Interrupt Disable Command Register 0x128 Interrupt Clear Command Register 0x12C Interrupt Set Command Register 0x130 End of Interrupt Command Register 0x134 Spurious Vector Register Note: AT91M42800A 86 AIC_SMR0 AIC_SMR1 AIC_SMR31 AIC_SVR0 AIC_SVR1 AIC_SVR31 AIC_IVR AIC_FVR AIC_ISR AIC_IPR AIC_IMR ...
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... AT91M42800A 26 25 – – – – – – PRIOR Code Label AIC_SRCTYPE_EXT_LOW_LEVEL AIC_SRCTYPE_EXT_NEGATIVE_EDGE AIC_SRCTYPE_EXT_HIGH_LEVEL AIC_SRCTYPE_EXT_POSITIVE_EDGE Code Label AIC_SRCTYPE_INT_LEVEL_SENSITIVE AIC_SRCTYPE_INT_EDGE_TRIGGERED 24 – ...
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... The IRQ Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The Source Vector Register (1 to 31) is indexed using the current interrupt number when the Interrupt Vector Register is read. When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU. AT91M42800A ...
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... FIQV FIQV FIQV – –– – – – – – – – – AT91M42800A – – – – – – – – – ...
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... Offset: 0x110 Reset Value: 0x0 31 30 IRQ0 IRQ1 23 22 – – PMC PIOB 7 6 TC1 TC0 • Interrupt Mask 0 = Corresponding interrupt is disabled Corresponding interrupt is enabled. AT91M42800A IRQ2 IRQ3 – – – – PIOA ST TC5 SPIB ...
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... NIRQ line inactive NIRQ line active. 1779D–ATARM–14-Apr- – – – – – – – – – – – – AT91M42800A – – – – – – – – – – NIRQ NFIQ 91 ...
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... AIC_IDCR Access Type: Write-only Offset: 0x124 31 30 IRQ0 IRQ1 23 22 – – PMC PIOB 7 6 TC1 TC0 • Interrupt Disable effect Disables corresponding interrupt. AT91M42800A IRQ2 IRQ3 – – – – PIOA ST TC5 SPIB ...
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... ST TC5 SPIB SPIA US1 IRQ2 IRQ3 – – – – PIOA ST TC5 SPIB SPIA US1 AT91M42800A – – – – – – TC4 TC3 TC2 US0 SW FIQ – – – – ...
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... Access Type: Read/Write Offset: 0x134 Reset Value • SPUVEC: Spurious Interrupt Vector Handler Address The user may store the address of the spurious interrupt handler in this register. AT91M42800A – – – – – – – ...
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... If another interrupt is pending, with lower or equal priority than old current level but with higher priority than the new current level, the NIRQ line is re-asserted, but the interrupt sequence does not immediately start because the I-bit is set in the core. AT91M42800A 95 ...
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... The Interrupt Handler can then proceed as required not necessary to save regis- 6. Finally, the Link Register (R14_fiq) is restored into the PC after decrementing Note: AT91M42800A 96 restored directly into the PC. This has effect of returning from the interrupt to what- ever was being executed before, and of loading the CPSR with the stored SPSR, masking or unmasking the interrupts depending on the state saved in the SPSR (the previous state of the ARM core) ...
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... PIO: Parallel I/O Controller The AT91M42800A has 54 programmable I/O lines. I/O lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins (see Tables page 100 cal PIO Controllers called PIOA and PIOB. Each PIO controller also provides an internal interrupt signal to the Advanced Interrupt Controller. ...
Page 98
... Registers PIO_MDER (Multi-Driver Enable) and PIO_MDDR (Multi-Driver Disable) control this option. Multi-driver can be selected whether the I/O pin is controlled by the PIO Controller or the peripheral. PIO_MDSR (Multi-Driver Status) indicates which pins are configured to support external drivers. AT91M42800A 98 1779D–ATARM–14-Apr-06 ...
Page 99
... Pad Pad Input Note: 1779D–ATARM–14-Apr- PIO_PSR PIO_MDSR Filter 1 0 OFF Value PIO_IFSR Event Detection PIO_IMR 1. See Section 15.8 ”PIO Connection Tables” on page AT91M42800A PIO_OSR 1 0 PIO_ODSR (1) PIO_PSR PIO_PDSR PIO_ISR 100. Peripheral Output Enable Peripheral Output ...
Page 100
... PA27 BMS 28 PA28 – 29 PA29 PME Note: 1. The OFF value is the default level seen on the peripheral input when the PIO line is enabled. AT91M42800A 100 Peripheral Signal Signal Description Direction External Interrupt 0 Input External Interrupt 1 Input External Interrupt 2 Input External Interrupt 3 ...
Page 101
... Timer3 Clock Signal Timer3 Signal A Bi-directional Timer3 Signal B Bi-directional Timer4 Clock Signal Timer4 Signal A Bi-directional Timer4 Signal B Bi-directional Timer5 Clock Signal Timer5 Signal A Bi-directional Timer5 Signal B Bi-directional AT91M42800A (1) OFF Value Reset State Output – NCS2 Output – NCS3 Output – A20 Output – ...
Page 102
... The reset value of this register depends on the level of the external pins at reset. 2. This register is cleared at reset. However, the first read of the register can give a value not equal to zero if any changes have occurred on any pins between the reset and the read. AT91M42800A 102 Name ...
Page 103
... P13 P12 P11 P29 P28 P27 P21 P20 P19 P13 P12 P11 AT91M42800A P26 P25 P24 P18 P17 P16 P10 P26 P25 P24 18 17 ...
Page 104
... P7 P6 This register indicates which pins are enabled for PIO control. This register is updated when PIO lines are enabled or dis- abled PIO is inactive on the corresponding line (peripheral is active PIO is active on the corresponding line (peripheral is inactive). AT91M42800A 104 P29 P28 P27 ...
Page 105
... P13 P12 P11 P29 P28 P27 P21 P20 P19 P13 P12 P11 AT91M42800A P26 P25 P24 P18 P17 P16 P10 P26 P25 P24 18 17 ...
Page 106
... This register shows the PIO pin control (output enable) status which is programmed in PIO_OER and PIO ODR. The defined value is effective only if the pin is controlled by the PIO. The register reads as follows The corresponding PIO is input on this line The corresponding PIO is output on this line. AT91M42800A 106 29 28 ...
Page 107
... P13 P12 P11 P29 P28 P27 P21 P20 P19 P13 P12 P11 AT91M42800A P26 P25 P24 P18 P17 P16 P10 P26 P25 P24 18 17 ...
Page 108
... P7 P6 This register indicates which pins have glitch filters selected updated when PIO outputs are enabled or disabled by writing to PIO_IFER or PIO_IFDR Filter is not selected on the corresponding input Filter is selected on the corresponding input (peripheral and PIO). AT91M42800A 108 P29 P28 P27 ...
Page 109
... P13 P12 P11 P29 P28 P27 P21 P20 P19 P13 P12 P11 AT91M42800A P26 P25 P24 P18 P17 P16 P10 P26 P25 P24 18 17 ...
Page 110
... This register shows the state of the physical pin of the chip. The pin values are always valid, regardless of whether the pins are enabled as PIO, peripheral, input or output. The register reads as follows The corresponding pin is at logic The corresponding pin is at logic 1. AT91M42800A 110 29 28 ...
Page 111
... P13 P12 P11 P29 P28 P27 P21 P20 P19 P13 P12 P11 AT91M42800A P26 P25 P24 P18 P17 P16 P10 P26 P25 P24 18 17 ...
Page 112
... The register is reset to zero following a read, and at reset input change has been detected on the corresponding pin since the register was last read least one input change has been detected on the corresponding pin since the register was last read. AT91M42800A 112 29 ...
Page 113
... P13 P12 P11 P29 P28 P27 P21 P20 P19 P13 P12 P11 AT91M42800A P26 P25 P24 P18 P17 P16 P10 P26 P25 P24 18 17 ...
Page 114
... P23 P22 15 14 P15 P14 This register indicates which pins are configured with open drain drivers PIO is not configured as an open drain PIO is configured as an open drain. AT91M42800A 114 P29 P28 P27 P21 P20 P19 13 12 ...
Page 115
... SF: Special Function Registers The AT91M42800A provides registers that implement the following special functions: • Chip Identification • RESET Status • Protect Mode (see 16.1 Chip Identification The AT91M42800A chip identifier is 0x14280041. SF User Interface Chip ID Base Address: 0xFFF00000 (Code Label SF_BASE) Table 16-1. ...
Page 116
... NVDSIZ: Nonvolatile Data Memory Size NVDSIZ Others • VDSIZ: Volatile Data Memory Size VDSIZ Others AT91M42800A 116 NVPTYP Size 0 None 1 32K Bytes 1 64K Bytes 1 128K Bytes ...
Page 117
... Chip ID has a single register definition without extensions extended Chip ID exists (to be defined in the future). 1779D–ATARM–14-Apr-06 Selected ARCH AT91x63yyy AT91x40yyy AT91x55yyy Type “M” Series or “F” Series “R” Series AT91M42800A Code Label: SF_ARCH SF_ARCH_AT91x63 SF_ARCH_AT91x40 SF_ARCH_AT91x55 Code Label: SF_NVPTYP SF_NVPTYP_M SF_NVPTYP_R 117 ...
Page 118
... RESET: Reset Status Information This field indicates whether the reset was demanded by the external system (via NRST the Watchdog internal reset request. Reset Cause of Reset 0x6C External Pin 0x53 Internal Watchdog AT91M42800A 118 – – – – ...
Page 119
... Used only when writing SF_PMR. PMRKEY reads 0. 0x27A8: Write access in SF_PMR is allowed. Other value: Write access in SF_PMR is prohibited. 1779D–ATARM–14-Apr- PMRKEY PMRKEY – – – AIC – – 85. AT91M42800A – – – – – – 119 ...
Page 120
... AT91M42800A 120 1779D–ATARM–14-Apr-06 ...
Page 121
... USART: Universal Synchronous/Asynchronous Receiver/Transmitter The AT91M42800A provides two identical, full-duplex, universal synchronous/asynchronous receiver/transmitters that interface to the APB and are connected to the Peripheral Data Controller. The main features are: • Programmable Baud Rate Generator with External or Internal Clock, as well as Slow Clock • Parity, Framing and Overrun Error Detection • ...
Page 122
... Baud Rate Clock is disabled. In Synchronous Mode with external clock selected (USCLKS = 3), the clock is provided directly by the signal on the SCK pin. No division is active. The value written in US_BRGR has no effect. AT91M42800A 122 1. After a hardware reset, the USART clock is disabled by default (see ment Controller” on page 55) ...
Page 123
... Each subsequent bit is sampled 16 cycles (1 bit period) after the previous one. Figure 17-3. Asynchronous Mode: Start Bit Detection 16 x Baud Rate Clock RXD Sampling 1779D–ATARM–14-Apr- 16-bit Counter OUT > SYNC True Start Detection AT91M42800A SYNC Divide Baud Rate Clock 1 D0 123 ...
Page 124
... Otherwise, the receiver waits for a first character and then initializes a counter which is decremented at each bit period and reloaded at each byte reception. When the counter reaches 0, the TIMEOUT bit in US_CSR is set. The user can restart the wait for a first character with the STTTO (Start Time-out) bit in US_CR. AT91M42800A 124 1-bit period ...
Page 125
... US_CR. In this case, the next byte written to US_THR will be transmit- ted as an address. After this any byte transmitted will have the parity bit cleared. 1779D–ATARM–14-Apr-06 Idle state duration between two characters Clock TXD Start Bit AT91M42800A = Time-guard Bit x Value Period Parity ...
Page 126
... The standard break transmission sequence is: 1. Wait for the transmitter ready 2. Send the STTBRK command 3. Wait for the transmitter ready 4. Send the STPBRK command The next byte can then be sent: AT91M42800A 126 (US_CSR.TXRDY = 1) (write 0x0200 to US_CR) (bit TXRDY = 1 in US_CSR) (write 0x0400 to US_CR) ...
Page 127
... When a bit is set in US_CSR and the same bit is set in US_IMR, the interrupt line is asserted. 17.9 Channel Modes The USART can be programmed to operate in three different test modes, using the field CHMODE in US_MR. 1779D–ATARM–14-Apr-06 (bit TXRDY = 1 in US_CSR) (write byte to US_THR) AT91M42800A 127 ...
Page 128
... The RXD pin level has no effect and the TXD pin is held high idle state. Remote loopback mode directly connects the RXD pin to the TXD pin. The Transmitter and the Receiver are disabled and have no effect. This mode allows bit-by-bit re-transmission. Figure 17-7. Channel Modes AT91M42800A 128 Automatic Echo Receiver ...
Page 129
... Receiver Time-out Register 0x28 Transmitter Time-guard Register 0x2C Reserved 0x30 Receive Pointer Register 0x34 Receive Counter Register 0x38 Transmit Pointer Register 0x3C Transmit Counter Register 1779D–ATARM–14-Apr-06 AT91M42800A Name Access US_CR Write-only US_MR Read/Write US_IER Write-only US_IDR Write-only US_IMR Read-only US_CSR ...
Page 130
... If break is not being transmitted, start transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. • STPBRK: Stop Break (Code Label US_STPBRK effect break is being transmitted, stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. AT91M42800A 130 – ...
Page 131
... No effect Start waiting for a character before clocking the time-out counter. • SENDA: Send Address (Code Label US_SENDA effect Multi-drop Mode only, the next character written to the US_THR is sent with the address bit set. 1779D–ATARM–14-Apr-06 AT91M42800A 131 ...
Page 132
... USART Mode Register Name: US_MR AT91M42800A 132 1779D–ATARM–14-Apr-06 ...
Page 133
... Slow Clock External (SCK) Character Length Five bits Six bits Seven bits Eight bits Parity Type Even Parity Odd Parity Parity forced to 0 (Space) Parity forced to 1 (Mark) No parity Multi-drop mode AT91M42800A 26 25 – – – – CLKO MODE9 10 9 PAR ...
Page 134
... MODE9: 9-Bit Character Length (Code Label US_MODE9 CHRL defines character length 9-Bit character length. • CKLO: Clock Output Select (Code Label US_CLKO The USART does not drive the SCK pin The USART drives the SCK pin. AT91M42800A 134 Synchronous (SYNC = 1) Code Label: US_NBSTOP 1 stop bit US_NBSTOP_1 ...
Page 135
... Enables TXEMPTY Interrupt. 1779D–ATARM–14-Apr- – – – – – – – – – OVRE ENDTX ENDRX AT91M42800A – – – – – – – TXEMPTY TIMEOUT RXBRK TXRDY RXRDY 135 ...
Page 136
... COMMTX: Enable ARM7TDMI ICE Debug Communication Channel Transmit Interrupt This bit is implemented for USART0 only effect Enables COMMTX Interrupt • COMMRX: Enable ARM7TDMI ICE Debug Communication Channel Receive Interrupt This bit is implemented for USART0 only effect Enables COMMRX Interrupt AT91M42800A 136 1779D–ATARM–14-Apr-06 ...
Page 137
... Disables TXEMPTY Interrupt. 1779D–ATARM–14-Apr- – – – – – – – – – OVRE ENDTX ENDRX AT91M42800A – – – – – – – TXEMPTY TIMEOUT RXBRK TXRDY RXRDY 137 ...
Page 138
... COMMTX: Disable ARM7TDMI ICE Debug Communication Channel Transmit Interrupt This bit is implemented for USART0 only effect Disables COMMTX Interrupt. • COMMRX: Disable ARM7TDMI ICE Debug Communication Channel Receive Interrupt This bit is implemented for USART0 only effect Disables COMMRX Interrupt. AT91M42800A 138 1779D–ATARM–14-Apr-06 ...
Page 139
... TXEMPTY Interrupt is Disabled. 1779D–ATARM–14-Apr- – – – – – – – – – OVRE ENDTX ENDRX AT91M42800A – – – – – – – TXEMPTY TIMEOUT RXBRK TXRDY RXRDY 139 ...
Page 140
... COMMTX: ARM7TDMI ICE Debug Communication Channel Transmit Interrupt Mask This bit is implemented for USART0 only COMMTX Interrupt is Disabled 1 = COMMTX Interrupt is Enabled • COMMRX: ARM7TDMI ICE Debug Communication Channel Receive Interrupt Mask This bit is implemented for USART0 only COMMRX Interrupt is Disabled 1 = COMMRX Interrupt is Enabled AT91M42800A 140 1779D–ATARM–14-Apr-06 ...
Page 141
... No parity bit has been detected false (or a parity bit high in multi-drop mode) since the last “Reset Status Bits” command. 1779D–ATARM–14-Apr- – – – – – – – – – OVRE ENDTX ENDRX AT91M42800A – – – – – – – TXEMPTY TIMEOUT RXBRK TXRDY RXRDY 141 ...
Page 142
... COMMTX: ARM7TDMI ICE Debug Communication Channel Transmit Status For USART0 only. Refer to the ARM7TDMI Datasheet for a complete description of this flag. • COMMRX: ARM7TDMI ICE Debug Communication Channel Receive Status For USART0 only. Refer to the ARM7TDMI Datasheet for a complete description of this flag. AT91M42800A 142 1779D–ATARM–14-Apr-06 ...
Page 143
... RXCHR – – – – – – – – – TXCHR AT91M42800A – – – – – – – – RXCHR – – – – ...
Page 144
... Baud Rate (Asynchronous Mode 2 to 65535 Baud Rate (Synchronous Mode) = Selected Clock/CD Notes Synchronous mode, the value programmed must be even to ensure a 50:50 mark:space ratio. 2. Clock divisor bypass ( must not be used when internal clock MCK is selected (USCLKS = 0). AT91M42800A 144 – ...
Page 145
... Time-out duration = Bit period 1779D–ATARM–14-Apr- – – – – – – – – – AT91M42800A – – – – – – – – – 145 ...
Page 146
... TG: Time-guard Value TG 0 Disables the TX Time-guard function 255 TXD is inactive high after the transmission of each character for the time-guard duration. Time-guard duration = TG x Bit period AT91M42800A 146 – – – – – – ...
Page 147
... RXPTR RXPTR RXPTR RXPTR – – – – – – RXCTR RXCTR AT91M42800A – – – – – – 147 ...
Page 148
... TXCTR: Transmit Counter TXCTR must be loaded with the size of the transmit buffer. 0: Stop Peripheral Data Transfer dedicated to the transmitter. 1-65535: Start Peripheral Data transfer if TXRDY is active. AT91M42800A 148 TXPTR TXPTR TXPTR ...
Page 149
... TC: Timer/Counter The AT91M42800A features two Timer/Counter blocks, each containing three identical 16-bit Timer/Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each Timer/Counter (TC) channel has 3 external clock inputs, 5 internal clock inputs, and 2 multi-purpose input/output signals which can be configured by the user ...
Page 150
... MCK/8 TIOA1 TIOA2 MCK/32 TCLK1 TCLK2 MCK/128 SLCK TCLK0 TCLK1 TIOA0 TIOA2 TCLK2 TCLK0 TCLK1 TCLK2 TIOA0 TIOA1 Timer Counter Block AT91M42800A 150 XC0 Timer/Counter TIOA Channel 0 XC1 TIOB XC2 TC0XC0S SYNC INT XC0 Timer/Counter TIOA Channel 1 XC1 TIOB XC2 SYNC ...
Page 151
... TIOB Signal for Channel 2 Description External Clock Inputs for Channels TIOA Signal for Channel 3 TIOB Signal for Channel 3 TIOA Signal for Channel 4 TIOB Signal for Channel 4 TIOA Signal for Channel 5 TIOB Signal for Channel 5 ”PMC: Power Management Controller” on page AT91M42800A 55). The 151 ...
Page 152
... The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2). Note: AT91M42800A 152 In all cases external clock is used, the duration of each of its levels must be longer than the system clock (MCK) period ...
Page 153
... Capture Mode (LDBSTOP = 1 in TC_CMR compare event in Waveform Mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands have effect only if the clock is enabled. 1779D–ATARM–14-Apr-06 CLKS MCK/2 MCK/8 MCK/32 MCK/128 SLCK XC0 XC1 XC2 BURST 1 AT91M42800A CLKI Selected Clock 153 ...
Page 154
... Mode, an external event can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by setting ENETRG in TC_CMR external trigger is used, the duration of the pulses must be longer than the system clock (MCK) period in order to be detected. AT91M42800A 154 Selected Trigger Clock ...
Page 155
... LDRBS: Load RB Status RB has been loaded at least once without any read, since the last read of the status • ETRGS: External Trigger Status An external trigger on TIOA or TIOB has been detected since the last read of the status 1779D–ATARM–14-Apr-06 AT91M42800A 155 ...
Page 156
TCCLKS MCK/2 MCK/8 MCK/32 MCK/128 SLCK XC0 XC1 XC2 BURST 1 SWTRG SYNC ABETRG ETRGEDG MTIOB Edge Detector TIOB MTIOA not loaded loaded TIOA Timer Counter Channel CLKSTA CLKI Capture ...
Page 157
... The following events control TIOA and TIOB: software trigger, external event and RC com- pare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR. 1779D–ATARM–14-Apr-06 AT91M42800A 157 ...
Page 158
... There has been a RC Compare match at least once since the last read of the status • COVFS: Counter Overflow Counter has attempted to count past $FFFF since the last read of the status • ETRGS: External Trigger External trigger has been detected since the last read of the status AT91M42800A 158 TIOA Event Software Trigger External Event ...
Page 159
TCCLKS MCK/2 CLKI MCK/8 MCK/32 MCK/128 SLCK XC0 XC1 XC2 BURST 1 CLK SWTRG SYNC Trig EEVT EEVTEDG ENETRG Edge Detector TIOB Timer Counter Channel CLKSTA CLKEN CLKDIS Q S CPCDIS CPCSTOP Register A Register B ...
Page 160
... Register A 0x18 Register B 0x1C Register C 0x20 Status Register 0x24 Interrupt Enable Register 0x28 Interrupt Disable Register 0x2C Interrupt Mask Register Note: 1. Read-only if WAVE = 0 AT91M42800A 160 Name Access See Table 8 See Table 8 See Table 8 TC_BCR Write-only TC_BMR Read/Write Name Access TC_CCR Write-only ...
Page 161
... Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 1779D–ATARM–14-Apr- – – – – – – – – – – – – AT91M42800A – – – – – – – – – – – SYNC 161 ...
Page 162
... TC1XC1S: External Clock Signal 1 Selection TC1XC1S • TC2XC2S: External Clock Signal 2 Selection TC2XC2S AT91M42800A 162 – – – – – – – – – TC2XC2S Signal Connected to XC0 ...
Page 163
... A software trigger is performed: the counter is reset and clock is started. 1779D–ATARM–14-Apr- – – – – – – – – – – – – AT91M42800A – – – – – – – – – SWTRG CLKDIS CLKEN 163 ...
Page 164
... LDBSTOP: Counter Clock Stopped with RB Loading (Code Label TC_LDBSTOP Counter clock is not stopped when RB loading occurs Counter clock is stopped when RB loading occurs. • LDBDIS: Counter Clock Disable with RB Loading (Code Label TC_LDBDIS Counter clock is not disabled when RB loading occurs Counter clock is disabled when RB loading occurs. AT91M42800A 164 – ...
Page 165
... Edge 0 0 None 0 1 Rising edge of TIOA 1 0 Falling edge of TIOA 1 1 Each edge of TIOA 1779D–ATARM–14-Apr-06 AT91M42800A Code Label: TC_ETRGEDG TC_ETRGEDG_EDGE_NONE TC_ETRGEDG_RISING_EDGE TC_ETRGEDG_FALLING_EDGE TC_ETRGEDG_BOTH_EDGE Code Label: TC_ABETRG TC_ABETRG_TIOB TC_ABETRG_TIOA Code Label: TC_LDRA TC_LDRA_EDGE_NONE TC_LDRA_RISING_EDGE TC_LDRA_FALLING_EDGE TC_LDRA_BOTH_EDGE Code Label: TC_LDRB ...
Page 166
... Counter clock is not stopped when counter reaches RC Counter clock is stopped when counter reaches RC. • CPCDIS: Counter Clock Disable with RC Compare (Code Label TC_CPCDIS Counter clock is not disabled when counter reaches RC Counter clock is disabled when counter reaches RC. AT91M42800A 166 ...
Page 167
... Set 1 0 Clear 1 1 Toggle 1779D–ATARM–14-Apr-06 External Event TIOB Direction (1) Input Output Output Output AT91M42800A Code Label: TC_EEVTEDG TC_EEVTEDG_EDGE_NONE TC_EEVTEDG_RISING_EDGE TC_EEVTEDG_FALLING_EDGE TC_EEVTEDG_BOTH_EDGE Code Label: TC_EEVT TC_EEVT_TIOB TC_EEVT_XC0 TC_EEVT_XC1 TC_EEVT_XC2 Code Label: TC_ACPA TC_ACPA_OUTPUT_NONE TC_ACPA_SET_OUTPUT TC_ACPA_CLEAR_OUTPUT TC_ACPA_TOGGLE_OUTPUT Code Label: TC_ACPC ...
Page 168
... Toggle • BEEVT: External Event Effect on TIOB BEEVT Effect 0 0 None 0 1 Set 1 0 Clear 1 1 Toggle AT91M42800A 168 Code Label: TC_AEEVT TC_AEEVT_OUTPUT_NONE TC_AEEVT_SET_OUTPUT TC_AEEVT_CLEAR_OUTPUT TC_AEEVT_TOGGLE_OUTPUT Code Label: TC_ASWTRG TC_ASWTRG_OUTPUT_NONE TC_ASWTRG_SET_OUTPUT TC_ASWTRG_CLEAR_OUTPUT TC_ASWTRG_TOGGLE_OUTPUT Code Label: TC_BCPB TC_BCPB_OUTPUT_NONE TC_BCPB_SET_OUTPUT TC_BCPB_CLEAR_OUTPUT TC_BCPB_TOGGLE_OUTPUT Code Label: TC_BCPC ...
Page 169
... BSWTRG: Software Trigger Effect on TIOB BSWTRG Effect 0 0 None 0 1 Set 1 0 Clear 1 1 Toggle 1779D–ATARM–14-Apr-06 AT91M42800A Code Label: TC_BSWTRG TC_BSWTRG_OUTPUT_NONE TC_BSWTRG_SET_OUTPUT TC_BSWTRG_CLEAR_OUTPUT TC_BSWTRG_TOGGLE_OUTPUT 169 ...
Page 170
... Access Type: Read-only Offset: 0x10 Reset Value: 0x0 31 30 – – – – • CV: Counter Value (Code Label TC_CV) CV contains the counter value in real time. AT91M42800A 170 – – – – – – ...
Page 171
... – – – – – – AT91M42800A – – – – – – – – – – – – ...
Page 172
... TC_RC Access Type: Read/Write Offset: 0x1C Reset Value: 0x0 31 30 – – – – • RC: Register C (Code Label TC_RC) RC contains the Register C value in real time. AT91M42800A 172 – – – – – – ...
Page 173
... TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. 1779D–ATARM–14-Apr- – – – – – – – – – LDRAS CPCS CPBS AT91M42800A – – – MTIOB MTIOA CLKSTA – – – CPAS LOVRS COVFS 173 ...
Page 174
... MTIOB: TIOB Mirror (Code Label TC_MTIOB TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high. AT91M42800A 174 1779D–ATARM–14-Apr-06 ...
Page 175
... TC Interrupt Enable Register Register Name: TC_IER 1779D–ATARM–14-Apr-06 AT91M42800A 175 ...
Page 176
... LDRAS: RA Loading (Code Label TC_LDRAS effect Enables the RA Load Interrupt. • LDRBS: RB Loading (Code Label TC_LDRBS effect Enables the RB Load Interrupt. • ETRGS: External Trigger (Code Label TC_ETRGS effect Enables the External Trigger Interrupt. AT91M42800A 176 – – – 21 ...
Page 177
... Disables the External Trigger Interrupt. 1779D–ATARM–14-Apr- – – – – – – – – – LDRAS CPCS CPBS AT91M42800A – – – – – – – – – CPAS LOVRS COVFS 177 ...
Page 178
... The Load RA Interrupt is enabled. • LDRBS: RB Loading (Code Label TC_LDRBS The Load RB Interrupt is disabled The Load RB Interrupt is enabled. • ETRGS: External Trigger (Code Label TC_ETRGS The External Trigger Interrupt is disabled The External Trigger Interrupt is enabled. AT91M42800A 178 – – – ...
Page 179
... SPI: Serial Peripheral Interface The AT91M42800A includes two SPIs which provide communication with external devices in master or slave mode. They are independent, and are referred to by the letters A and B. 19.1 Pin Description Seven pins are associated with the SPI Interface. When not needed for the SPI function, each of these pins can be configured as a PIO ...
Page 180
... Model” on page 19.2.1 Fixed Peripheral Select This mode is ideal for transferring memory blocks without the extra overhead in the transmit data register to determine the peripheral. AT91M42800A 180 Generic Mnemonic Mode Function Serial data input to SPI ...
Page 181
... A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCSA/NSS signal. When a mode fault is detected, the MODF bit in the SP_SR is set until the SP_SR is read and the SPI is disabled until re-enabled by bit SPIEN in the SP_CR (Control Register). 1779D–ATARM–14-Apr-06 AT91M42800A 181 ...
Page 182
... PS Variable peripheral 1 NPCS = SP_TDR(PCS) Delay DLYBS Serializer = SP_TDR(TD) TDRE = 1 Data Transfer SP_RDR(RD) = Serializer RDRF = 1 Delay DLYBCT TDRE 1 NPCS = 0xF Delay DLYBCS AT91M42800A 182 1 0 Fixed peripheral NPCS = SP_MR(PCS Variable peripheral SP_TDR(PCS) New peripheral NPCS = 0xF Delay DLYBCS NPCS = SP_TDR(PCS) 0 ...
Page 183
... SPIDIS SPIEN MISO SP_MR(PS SP_MR(PCS) 1779D–ATARM–14-Apr-06 SPCK Clock Generator SPI SP_CSRx[15:0] Clock SP_RDR PCS RD MSB LSB Serializer SP_TDR PCS TD SP_MR(MSTR) AT91M42800A SPCK MOSI NPCS3 NPCS2 NPCS1 NPCS0 SP_SR ...
Page 184
... In slave mode CPOL, NCPHA and BITS fields of SP_CSR0 are used to define the transfer characteristics. The other Chip Select Registers are not used in slave mode. Figure 19-4. SPI in Slave Mode SPCK NSS SPIDIS SPIEN S R MOSI AT91M42800A 184 Q SP_RDR RD LSB MSB Serializer SP_TDR TD ...
Page 185
... MOSI (from Master) MSB MISO MSB (from Slave) X NSS (to Slave) 1779D–ATARM–14-Apr- AT91M42800A LSB 2 1 LSB LSB 2 1 LSB 185 ...
Page 186
... TDRE. When a transfer is performed, the counter is decremented and the pointer is incremented. When the counter reaches 0, the status bit is set (SPENDRX for the receiver, SPENDTX for the transmitter in SP_SR) and can be programmed to generate an interrupt. While the counter is at zero, the status bit is asserted and transfers are disabled. AT91M42800A 186 No change of peripheral ...
Page 187
... Transmit Pointer Register 0x2C Transmit Counter Register 0x30 Chip Select Register 0 0x34 Chip Select Register 1 0x38 Chip Select Register 2 0x3C Chip Select Register 3 1779D–ATARM–14-Apr-06 AT91M42800A Name Access SP_CR Write-only SP_MR Read/Write SP_RDR Read-only SP_TDR Write-only SP_SR Read-only ...
Page 188
... If a transfer is in progress, the transfer is finished before the SPI is disabled. If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled. • SWRST: SPI Software reset (Code Label SP_SWRST effect Resets the SPI. A software triggered hardware reset of the SPI interface is performed. AT91M42800A 188 – ...
Page 189
... PCS: Peripheral Chip Select (Code Label SP_PCS) 1779D–ATARM–14-Apr- DLYBCS – – – – – – – MCK32 (1) . AT91M42800A PCS 10 9 – – PCSDEC PS Code Label: SP_PS SP_PS_FIXED SP_PS_VARIABLE – 0 MSTR 189 ...
Page 190
... If DLYBCS is less than or equal to six, six SPI Master Clock periods will be inserted by default. Otherwise, the following equation determines the delay: Delay_ Between_Chip_Selects = DLYBCS • SPI_Master_Clock_period AT91M42800A 190 1779D–ATARM–14-Apr-06 ...
Page 191
... In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero. 1779D–ATARM–14-Apr- – – – – – AT91M42800A – – – PCS 191 ...
Page 192
... This field is only used if Variable Peripheral Select is active ( and if the SPI is in Master Mode. If PCSDEC = 0: PCS = xxx0 NPCS[3:0] = 1110 PCS = xx01 NPCS[3:0] = 1101 PCS = x011 NPCS[3:0] = 1011 PCS = 0111 NPCS[3:0] = 0111 PCS = 1111 forbidden (no peripheral is selected don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS AT91M42800A 192 – – – – ...
Page 193
... SPIENS: SPI Enable Status (Code Label SP_SPIENS SPI is disabled SPI is enabled. 1779D–ATARM–14-Apr- – – – – – – SPENDTX SPENDRX OVRES AT91M42800A – – – – – – – – – ...
Page 194
... SPENDRX: End of Receiver Transfer Interrupt Enable (Code Label SP_SPENDRX effect Enables the End of Receiver Transfer Interrupt. • SPENDTX: End of Transmitter Transfer Interrupt Enable (Code Label SP_SPENDTX effect Enables the End of Transmitter Transfer Interrupt. AT91M42800A 194 – – ...
Page 195
... SPENDTX: End of Transmitter Transfer Interrupt Disable (Code Label SP_SPENDTX effect Disables the End of Transmitter Transfer Interrupt. 1779D–ATARM–14-Apr- – – – – – – SPENDTX SPENDRX OVRES AT91M42800A – – – – – – – – – ...
Page 196
... SPENDRX: End of Receiver Transfer Interrupt Mask (Code Label SP_SPENDRX End of Receiver Transfer Interrupt is disabled End of Receiver Transfer Interrupt is enabled. • SPENDTX: End of Transmitter Transfer Interrupt Mask (Code Label SP_SPENDTX End of Transmitter Transfer Interrupt is disabled End of Transmitter Transfer Interrupt is enabled. AT91M42800A 196 – ...
Page 197
... RXPTR RXPTR RXPTR RXPTR – – – – – – RXCTR RXCTR AT91M42800A – – – – – – 197 ...
Page 198
... TXCTR: Transmit Counter TXCTR must be loaded with the size of the transmit buffer. 0: Stop Peripheral Data Transfer dedicated to the transmitter. 1-65535: Start Peripheral Data transfer if TDRE is active. AT91M42800A 198 TXPTR TXPTR TXPTR ...
Page 199
... DLYBS SCBR – Bits Per Transfer Reserved Reserved Reserved Reserved Reserved Reserved Reserved AT91M42800A – NCPHA CPOL Code Label: SP_BITS SP_BITS_8 SP_BITS_9 SP_BITS_10 SP_BITS_11 SP_BITS_12 SP_BITS_13 SP_BITS_14 SP_BITS_15 SP_BITS_16 – ...
Page 200
... The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, a delay of four SPI Master Clock periods are inserted. Otherwise, the following equation determines the delay: Delay_After_Transfer = 32 • DLYBCT • SPI_Master_Clock_period AT91M42800A 200 2 x SCBR 1779D–ATARM–14-Apr-06 ...