M42800A Atmel Corporation, M42800A Datasheet - Page 14

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7.6.2
7.6.3
7.7
7.7.1
7.7.2
14
Memory Controller
AT91M42800A
Embedded ICE
IEEE 1149.1 JTAG Boundary Scan
Protection Mode
Internal Memories
Standard RS232 drivers generally contain internal 400 k pull-up resistors. If TXD1 is con-
nected to one of these drivers, this pull-up will ensure normal operation, without the need for
an additional external resistor.
ARM standard embedded in-circuit emulation is supported via the JTAG/ICE port. It is con-
nected to a host computer via an embedded ICE Interface.
Embedded ICE mode is selected when MODE1 is low.
It is not possible to switch directly between ICE and JTAG operations. A chip reset must be
performed (NRST and NTRST) after MODE0 and/or MODE1 have/has been changed. The
reset input to the embedded ICE (NTRST) is provided separately to facilitate debug of boot
programs.
IEEE 1149.1 JTAG Boundary Scan is enabled when MODE0 is low and MODE1 is high. The
functions SAMPLE, EXTEST and BYPASS are implemented. In ICE Debug mode, the ARM
core responds with a non-JTAG chip ID that identifies the core to the ICE system. This is not
IEEE 1149.1 JTAG compliant. It is not possible to switch directly between JTAG and ICE oper-
ations. A chip reset must be performed (NRST and NTRST) after MODE0 and/or MODE1
have/has been changed.
The ARM7TDMI processor address space is 4G bytes. The memory controller decodes the
internal 32-bit address bus and defines three address spaces:
In any of these address spaces, the ARM7TDMI operates in little-endian mode only.
The embedded peripherals can be protected against unwanted access. The PME (Protect
Mode Enable) pin must be tied high and validated in its peripheral operation (PIO Disable) to
enable the protection mode. When enabled, any peripheral access must be done while the
ARM7TDMI is running in Privileged mode (i.e., the accesses in user mode result in an abort).
Only the valid peripheral address space is protected and requests to the undefined addresses
will lead to a normal operation without abort.
The AT91M42800A microcontroller integrates an 8-Kbyte primary internal SRAM. All internal
memories are 32 bits wide and single-clock cycle accessible. Byte (8-bit), half-word (16-bit) or
word (32-bit) accesses are supported and are executed within one cycle. Fetching Thumb or
ARM instructions is supported and internal memory can store twice as many Thumb instruc-
tions as ARM ones.
The SRAM bank is mapped at address 0x0 (after the remap command), and ARM7TDMI
exception vectors between 0x0 and 0x20 that can be modified by the software. The rest of the
• Internal Memories in the four lowest megabytes
• Middle Space reserved for the external devices (memory or peripherals) controlled by the
• Internal Peripherals in the four highest megabytes
EBI
1779D–ATARM–14-Apr-06