M42800A Atmel Corporation, M42800A Datasheet - Page 32

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

11.11 Wait States
11.11.1
32
AT91M42800A
Standard Wait States
It is therefore necessary to avoid excessive loading of the NWE pins, which could delay the
write signal too long and cause a contention with a subsequent read cycle in standard
protocol.
Figure 11-12. Data Hold Time
In early read protocol the data can remain valid longer than in standard read protocol due to
the additional wait cycle which follows a write access.
The EBI can automatically insert wait states. The different types of wait states are listed below:
Each chip select can be programmed to insert one or more wait states during an access on
the corresponding device. This is done by setting the WSE field in the corresponding
EBI_CSR. The number of cycles to insert is programmed in the NWS field in the same
register.
Below is the correspondence between the number of standard wait states programmed and
the number of cycles during which the NWE pulse is held low:
For each additional wait state programmed, an additional cycle is added.
• Standard wait states
• Data float wait states
• External wait states
• Chip select change wait states
• Early Read wait states (as described in
0 wait states
1 wait state
Data Output
ADDR
MCKI
NWE
1/2 cycle
1 cycle
”Read Protocols” on page
29)
1779D–ATARM–14-Apr-06