M42800A Atmel Corporation, M42800A Datasheet - Page 95

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

14.25 Standard Interrupt Sequence
1779D–ATARM–14-Apr-06
It is assumed that:
When NIRQ is asserted, if the bit I of CPSR is 0, the sequence is:
• The Advanced Interrupt Controller has been programmed, AIC_SVR are loaded with
• The Instruction at address 0x18(IRQ exception vector address) is
1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded
2. The ARM core enters IRQ mode, if it is not already.
3. When the instruction loaded at address 0x18 is executed, the Program Counter is
4. The previous step has effect to branch to the corresponding interrupt service routine.
5. Further interrupts can then be unmasked by clearing the I-bit in the CPSR, allowing
6. The Interrupt Handler can then proceed as required, saving the registers which will
7. The I-bit in the CPSR must be set in order to mask interrupts before exiting, to ensure
8. The End of Interrupt Command Register (AIC_EOICR) must be written in order to
corresponding interrupt service routine addresses and interrupts are enabled.
ldr pc, [pc, #-&F20]
in the IRQ link register (R14_irq) and the Program Counter (R15) is loaded with 0x18.
In the following cycle during fetch at address 0x1C, the ARM core adjusts R14_irq,
decrementing it by 4.
loaded with the value read in AIC_IVR. Reading the AIC_IVR has the following
effects:
– Set the current interrupt to be the pending one with the highest priority. The current
– De-assert the NIRQ line on the processor. (Even if vectoring is not used, AIC_IVR
– Automatically clear the interrupt, if it has been programmed to be edge triggered.
– Push the current level on to the stack.
– Return the value written in the AIC_SVR corresponding to the current interrupt.
This should start by saving the Link Register(R14_irq) and the SPSR(SPSR_irq).
Note that the Link Register must be decremented by 4 when it is saved, if it is to be
restored directly into the Program Counter at the end of the interrupt.
re-assertion of the NIRQ to be taken into account by the core. This can occur if an
interrupt with a higher priority than the current one occurs.
be used and restoring them at the end. During this phase, an interrupt of priority
higher than the current level will restart the sequence from step 1. Note that if the
interrupt is programmed to be level sensitive, the source of the interrupt must be
cleared during this phase.
that the interrupt is completed in an orderly manner.
indicate to the AIC that the current interrupt is finished. This causes the current level
to be popped from the stack, restoring the previous current level if one exists on the
stack. If another interrupt is pending, with lower or equal priority than old current level
but with higher priority than the new current level, the NIRQ line is re-asserted, but
the interrupt sequence does not immediately start because the I-bit is set in the core.
level is the priority level of the current interrupt.
must be read in order to de-assert NIRQ)
AT91M42800A
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