M42800A Atmel Corporation, M42800A Datasheet - Page 23

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

11. EBI: External Bus Interface
11.1
1779D–ATARM–14-Apr-06
External Memory Mapping
The EBI handles the access requests performed by the ARM core or the PDC. It generates the
signals that control the access to the external memory or peripheral devices. The EBI is fully
programmable and can address up to 64M bytes. It has eight chip selects and a 24-bit address
bus, the upper four bits of which are multiplexed with a chip select.
The 16-bit data bus can be configured to interface with 8- or 16-bit external devices. Separate
read and write control signals allow for direct memory and peripheral interfacing.
The EBI supports different access protocols allowing single clock cycle memory accesses.
The main features are:
The EBI User Interface is described on page 48.
The memory map associates the internal 32-bit address space with the external 24-bit
address bus.
The memory map is defined by programming the base address and page size of the external
memories (see registers EBI_CSR0 to EBI_CSR7 in
page
memory.
If the physical memory device is smaller than the programmed page size, it wraps around and
appears to be repeated within the page. The EBI correctly handles any valid access to the
memory device within the page (see
In the event of an access request to an address outside any programmed page, an abort sig-
nal is generated. Two types of abort are possible: instruction prefetch abort and data abort.
The corresponding exception vector addresses are 0x0000000C and 0x00000010, respec-
tively. It is up to the system programmer to program the error handling routine to use in case of
an abort (see the ARM7TDMI datasheet for further information).
The chip selects can be defined to the same base address and an access to the overlapping
address space asserts both NCS lines. The Chip Select Register, having the smaller number,
defines the characteristics of the external access and the behaviour of the control signals.
• External memory mapping
• Up to 8 chip select lines
• 8- or 16-bit data bus
• Byte write or byte select lines
• Remap of boot memory
• Two different read protocols
• Programmable wait state generation
• External wait request
• Programmable data float time
48). Note that A0 - A23 is only significant for 8-bit memory; A1 - A23 is used for 16-bit
Figure 11-1 on page
Section 11.13 ”EBI User Interface” on
24).
AT91M42800A
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