M42800A Atmel Corporation, M42800A Datasheet - Page 12

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7.3
7.4
7.5
7.5.1
12
Operating Modes
Clock Generator
Reset
AT91M42800A
NRST Pin
The AT91M42800A has two pins dedicated to defining MODE0 and MODE1 operating modes.
These pins allow the user to enter the device in Boundary Scan mode. They also allow the
user to run the processor from the on-chip oscillator output and from an external clock by
bypassing the on-chip oscillator. The last mode is reserved for test purposes. A chip reset
must be performed (NRST and NTRST) after MODE0 and/or MODE1 have been changed.
Table 7-1.
Warning: The user must take the external oscillator frequency into account so that it is consis-
tent with the minimum access time requested by the memory device used at the boot. Both the
default EBI setting (zero wait state) on Chip Select 0 (See
the minimum access time of the boot memory are two parameters that determine this maxi-
mum frequency of the external oscillator.
The AT91M42800A microcontroller embeds a 32.768 kHz oscillator that generates the Slow
Clock (SLCK). This on-chip oscillator can be bypassed by setting the correct logical level on
the MODE0 and MODE1 pins, as shown above. In this case, SLCK equals XIN.
The AT91M42800A microcontroller has a fully static design and works either on the Master
Clock (MCK), generated from the Slow Clock by means of the two integrated PLLs, or on the
Slow Clock (SLCK).
These clocks are also provided as an output of the device on the pin MCKO, which is multi-
plexed with a general-purpose I/O line. While NRST is active, and after the reset, the MCKO is
valid and outputs an image of the SLCK signal. The PIO Controller must be programmed to
use this pin as standard I/O line.
Reset initializes the user interface registers to their default states as defined in the peripheral
sections of this datasheet and forces the ARM7TDMI to perform the next instruction fetch from
address zero. Except for the program counter, the ARM core registers do not have defined
reset states. When reset is active, the inputs of the AT91M42800A must be held at valid logic
levels. The EBI address lines drive low during reset. All the peripheral clocks are disabled dur-
ing reset to save power.
NRST is the active low reset input. It is asserted asynchronously, but exit from reset is syn-
chronized internally to the slow clock (SLCK). At power-up, NRST must be active until the on-
chip oscillator is stable. During normal operation, NRST must be active for a minimum of 10
SLCK clock cycles to ensure correct initialization.
MODE0
0
0
1
1
MODE1
0
1
0
1
Operating Mode
Normal operating mode by using the on-chip oscillator
Boundary Scan Mode
Normal operating mode by using an external clock on XIN
Reserved for test
”Boot on NCS0” on page
1779D–ATARM–14-Apr-06
29) and