M42800A Atmel Corporation, M42800A Datasheet - Page 81
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
M42800A
Manufacturer Part Number
M42800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M42800A.pdf
(224 pages)
4.M42800A.pdf
(27 pages)
Specifications of M42800A
Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
54
Usb Speed
No
Usb Interface
No
Spi
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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14. AIC: Advanced Interrupt Controller
Figure 14-1. Interrupt Controller Block Diagram
1779D–ATARM–14-Apr-06
External Interrupt Sources
Internal Interrupt Sources
Advanced Peripheral
FIQ Source
Bus (APB)
The AT91M42800A has an 8-level priority, individually maskable, vectored interrupt controller.
This feature substantially reduces the software and real-time overhead in handling internal
and external interrupts.
The interrupt controller is connected to the NFIQ (fast interrupt request) and the NIRQ (stan-
dard interrupt request) inputs of the ARM7TDMI processor. The processor’s NFIQ line can
only be asserted by the external fast interrupt request input: FIQ. The NIRQ line can be
asserted by the interrupts generated by the on-chip peripherals and the external interrupt
request lines: IRQ0 to IRQ3.
The 8-level priority encoder allows the customer to define the priority between the different
NIRQ interrupt sources.
Internal sources are programmed to be level sensitive or edge triggered. External sources can
be programmed to be positive or negative edge triggered or high- or low-level sensitive.
The interrupt sources are listed in Table 14-1 and the AIC programmable registers in Table 6.
Note:
After a hardware reset, the external interrupt sources pins are controlled by the Controller. They
must be configured to be controlled by the peripheral before being used.
Memorization
Memorization
Control
Logic
Prioritization
Controller
Manager
Manager
NFIQ
NIRQ
NIRQ
NFIQ
AT91M42800A
ARM7TDMI
Core
81
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