M42800A Atmel Corporation, M42800A Datasheet - Page 17

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

8.0.3
8.1
8.1.1
8.1.2
1779D–ATARM–14-Apr-06
System Peripherals
Peripheral Data Controller
PMC: Power Management Controller
ST: System Timer
the result is then ORed to generate the Interrupt Source signal to the Advanced Interrupt
Controller.
The interrupt mask is read in the Interrupt Mask Register and is modified with the Interrupt
Enable Register and the Interrupt Disable Register. The enable/disable/status (or mask)
makes it possible to enable or disable peripheral interrupt sources with a non-interruptible sin-
gle instruction. This eliminates the need for interrupt masking at the AIC or Core level in real-
time and multi-tasking systems.
The AT91M42800A has an 8-channel PDC dedicated to the two on-chip USARTs and to the
two on-chip SPIs. One PDC channel is connected to the receiving channel and one to the
transmitting channel of each peripheral.
The user interface of a PDC channel is integrated in the memory space of each USART chan-
nel and in the memory space of each SPI. It contains a 32-bit address pointer register and a
16-bit count register. When the programmed data is transferred, an end-of-transfer interrupt is
generated by the corresponding peripheral. See
nous/Asynchronous Receiver/Transmitter” on page 121
Peripheral Interface” on page 177
The AT91M42800A’s Power Management Controller optimizes the power consumption of the
device. The PMC controls the clocking elements such as the oscillator and the PLLs, and the
System and the Peripheral Clocks. It also controls the MCKO pin and permits to the user to
select four different signals to be driven on this pin.
The AT91M42800A has the following clock elements:
The on-chip low-power oscillator together with the PLL-based frequency multiplier and the
prescaler results in a programmable clock between 500 Hz and 66 MHz. It is the responsibility
of the user to make sure that the PMC programming does not result in a clock over the accept-
able limits.
The System Timer module integrates three different free-running timers:
• The oscillator providing a clock that depends on the crystal fundamental frequency
• PLL A providing a low-to-middle frequency clock range
• PLL B providing a middle-to-high frequency range
• The Clock prescaler
• The ARM Processor Clock controller
• The Peripheral Clock controller
• The Master Clock Output controller
• A Period Interval Timer setting the base time for an Operating System.
connected between the XIN and XOUT pins
for more details on PDC operation and programming.
Section 17. ”USART: Universal Synchro-
and
AT91M42800A
Section 19. ”SPI: Serial
17