M42800A Atmel Corporation, M42800A Datasheet - Page 98

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

15.5
15.6
15.7
98
Interrupts
User Interface
Multi-driver (Open Drain)
AT91M42800A
Each parallel I/O can be programmed to generate an interrupt when a level change occurs.
This is controlled by the PIO_IER (Interrupt Enable) and PIO_IDR (Interrupt Disable) registers
which enable/disable the I/O interrupt by setting/clearing the corresponding bit in the
PIO_IMR. When a change in level occurs, the corresponding bit in the PIO_ISR (Interrupt Sta-
tus) is set whether the pin is used as a PIO or a peripheral and whether it is defined as input or
output. If the corresponding interrupt in PIO_IMR (Interrupt Mask) is enabled, the PIO interrupt
is asserted.
When PIO_ISR is read, the register is automatically cleared.
Each individual I/O is associated with a bit position in the Parallel I/O user interface registers.
Each of these registers are 32 bits wide. If a parallel I/O line is not defined, writing to the corre-
sponding bits has no effect. Undefined bits read zero.
Each I/O can be programmed for multi-driver option. This means that the I/O is configured as
open drain (can only drive a low level) in order to support external drivers on the same pin. An
external pull-up is necessary to guarantee a logic level of one when the pin is not being driven.
Registers PIO_MDER (Multi-Driver Enable) and PIO_MDDR (Multi-Driver Disable) control this
option. Multi-driver can be selected whether the I/O pin is controlled by the PIO Controller or
the peripheral. PIO_MDSR (Multi-Driver Status) indicates which pins are configured to support
external drivers.
1779D–ATARM–14-Apr-06