M42800A Atmel Corporation, M42800A Datasheet - Page 123

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 17-2. Baud Rate Generator
17.3
17.3.1
Figure 17-3. Asynchronous Mode: Start Bit Detection
1779D–ATARM–14-Apr-06
MCK/8
SLCK
Receiver
MCK
SCK
Asynchronous Receiver
Rate Clock
16 x Baud
Sampling
USCLKS
RXD
0
1
The USART is configured for asynchronous operation when SYNC = 0 (bit 7 of US_MR). In
asynchronous mode, the USART detects the start of a received character by sampling the
RXD signal until it detects a valid start bit. A low level (space) on RXD is interpreted as a valid
start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the
baud rate. Hence a space which is longer than 7/16 of the bit period is detected as a valid start
bit. A space which is 7/16 of a bit period or shorter is ignored and the receiver continues to
wait for a valid start bit.
When a valid start bit has been detected, the receiver samples the RXD at the theoretical mid-
point of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (one bit
period) so the sampling point is 8 cycles (0.5 bit periods) after the start of the bit. The first sam-
pling point is therefore 24 cycles (1.5 bit periods) after the falling edge of the start bit was
detected. Each subsequent bit is sampled 16 cycles (1 bit period) after the previous one.
CLK
16-bit Counter
CD
True Start
Detection
OUT
0
SYNC
CD
>1
1
0
0
1
Divide
by 16
SYNC
AT91M42800A
0
1
D0
Baud Rate
Clock
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