M42800A Atmel Corporation, M42800A Datasheet - Page 57

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

12.2.2
12.2.3
1779D–ATARM–14-Apr-06
PLL Selection
Source Clock Selection
order filter. The PLLRC pin (A or B) that corresponds to the PLL that is disabled may be
grounded if capacitors and resistors need to be saved.
Figure 12-5. PLL Capacitors and Resistors
Typical values for the two PLLs are shown below:
With these parameters, the output frequency is stable (±10%) in 600 µs. This settling time is
the value to be programmed in the PLLCOUNT field of PMC_CGMR. The maximum frequency
overshoot during this phase is 22.5 MHz.
With these parameters, the output frequency is stable (±10%) in 4 ms. This settling time is the
value to be programmed in the PLLCOUNT field of PMC_CGMR. The maximum frequency
overshoot during this phase is 38 MHz.
The required PLL must be selected at the first writing access and cannot be changed after
that. The PLLS bit in PMC_CGMR (Clock Generator Mode Register) determines which PLL
module is activated. The other PLL is disabled in order to reduce power consumption and can
only be activated by another reset. Writing in PMC_CGMR with a different value has no effect.
The bit CSS in PMC_CGMR selects the Slow Clock or the output of the activated PLL as the
Source Clock of the prescaler. After reset, the CSS field is 0, selecting the Slow Clock as
Source Clock.
When switching from Slow Clock to PLL Output, the Source Clock takes effect after 3 Slow
Clock cycles plus 2.5 PLL output signal cycles. This is a maximum value.
PLLA:
PLLB:
F
F
R = 1600 Ohm
C = 100 nF
C
F
F
R = 800 Ohm
C = 1 µF
C
SCLK
out
SCLK
out
2
2
= 10 nF
= 100 nF
_PLLA = 16.776 MHz
_PLLB = 33.554 MHz
= 32.768 kHz
= 32.768 kHz
C2
C
R
PLLRC
GND
PLL
AT91M42800A
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