M42800A Atmel Corporation, M42800A Datasheet - Page 124

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 17-4. Asynchronous Mode: Character Reception
17.3.2
17.3.3
17.3.4
17.3.5
17.3.6
124
AT91M42800A
Synchronous Receiver
Receiver Ready
Parity Error
Framing Error
Time-out
Example: 8-bit, parity enabled 1 stop
Sampling
RXD
When configured for synchronous operation (SYNC = 1), the receiver samples the RXD signal
on each rising edge of the Baud Rate clock. If a low level is detected, it is considered as a
start. Data bits, parity bit and stop bit are sampled and the receiver waits for the next start bit.
See example in Figure 17-5.
Figure 17-5. Synchronous Mode: Character Reception
When a complete character is received, it is transferred to the US_RHR and the RXRDY sta-
tus bit in US_CSR is set. If US_RHR has not been read since the last transfer, the OVRE
status bit in US_CSR is set.
Each time a character is received, the receiver calculates the parity of the received data bits,
in accordance with the field PAR in US_MR. It then compares the result with the received par-
ity bit. If different, the parity error bit PARE in US_CSR is set.
If a character is received with a stop bit at low level and with at least one data bit at high level,
a framing error is generated. This sets FRAME in US_CSR.
This function allows an idle condition on the RXD line to be detected. The maximum delay for
which the USART should wait for a new character to arrive while the RXD line is inactive (high
level) is programmed in US_RTOR (Receiver Tim-out). When this register is set to 0, no time-
out is detected. Otherwise, the receiver waits for a first character and then initializes a counter
which is decremented at each bit period and reloaded at each byte reception. When the
counter reaches 0, the TIMEOUT bit in US_CSR is set. The user can restart the wait for a first
character with the STTTO (Start Time-out) bit in US_CR.
0.5-bit
period
True Start Detection
Example: 8-bit, parity enabled 1 stop
Sampling
period
1-bit
RXD
SCK
D0
True Start Detection
D1
D2
D0
D3
D1
D4
D2
D5
D3
D6
D4
D7
D5
Parity Bit
D6
Stop Bit
D7
1779D–ATARM–14-Apr-06
Parity Bit
Stop Bit