M42800A Atmel Corporation, M42800A Datasheet - Page 75

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M42800A

Manufacturer Part Number
M42800A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of M42800A

Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
54
Usb Speed
No
Usb Interface
No
Spi
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
13.6
Register Name:
Access Type:
Offset:
Reset Value:
• PIV: Period Interval Value
Defines the value loaded in the 16-bit counter of the Period Interval Timer. The maximum period is obtained by program-
ming PIV at 0x0 corresponding to 65536 Slow Clock cycles.
13.7
Register Name:
Access Type:
Offset:
Reset Value:
• WDV: Watchdog Counter Value
Defines the value loaded in the 16-bit counter. The maximum period is obtained by programming WDV to 0x0 correspond-
ing to 65536 • 128 Slow Clock cycles.
• RSTEN: Reset Enable
0 = No reset is generated when a watchdog overflow occurs.
1 = An internal reset is generated when a watchdog overflow occurs.
• EXTEN: External Signal Assertion Enable
0 = The NWDOVF is not tied low when a watchdog overflow occurs.
1 = The NWDOVF is tied low during 8 Slow Clock cycles when a watchdog overflow occurs.
1779D–ATARM–14-Apr-06
31
23
15
31
23
15
7
7
System Timer Period Interval Mode Register
System Timer Watchdog Mode Register
ST_PIMR
Read/Write
0x04
0x0
30
22
14
ST_WDMR
Read/Write
0x08
0x0002 0000
30
22
14
6
6
29
21
13
29
21
13
5
5
28
20
12
28
20
12
4
4
WDV
WDV
PIV
PIV
27
19
11
27
19
11
3
3
26
18
10
26
18
10
2
2
AT91M42800A
EXTEN
25
17
25
17
9
1
9
1
RSTEN
24
16
24
16
8
0
8
0
75

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