M42800A Atmel Corporation, M42800A Datasheet - Page 24

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

11.2
11.3
24
Abort Status
EBI Behavior During Internal Accesses
AT91M42800A
Figure 11-1. External Memory Smaller than Page Size
When an abort is generated, the EBI_AASR (Abort Address Status Register) and the
EBI_ASR (Abort Status Register) provide the details of the source causing the abort. Only the
last abort is saved and registers are left in the last abort status. After the reset, the registers
are initialized to 0.
The following are saved:
In EBI_AASR:
In EBI_ASR:
When the ARM core performs accesses in the internal memories or the embedded peripher-
als, the EBI signals behave as follows:
• The address at which the abort is generated
• Whether or not the processor has accessed an undefined address in the EBI address
• Whether or not the processor required an access at a misaligned address
• The size of the access (byte, word or half-word)
• The type of the access (read, write or code fetch)
• The address lines remain at the level of the last external access.
• The data bus is tri-stated.
• The control signals remain in an inactive state.
space
Memory
Map
1M Byte Device
1M Byte Device
1M Byte Device
1M Byte Device
Low
Low
Low
Low
Hi
Hi
Hi
Hi
Base + 4M Bytes
Base + 3M Bytes
Base + 2M Bytes
Base + 1M Byte
Base
Repeat 3
Repeat 2
Repeat 1
1779D–ATARM–14-Apr-06