M42800A Atmel Corporation, M42800A Datasheet - Page 13

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7.5.2
7.5.3
7.6
7.6.1
1779D–ATARM–14-Apr-06
Emulation Functions
NTRST Pin
Watchdog Reset
Tri-state Mode
The pins BMS and NTRI are sampled during the 10 SLCK clock cycles just prior to the rising
edge of NRST.
The NRST pin has no effect on the on-chip Embedded ICE logic.
The NTRST control pin initializes the selected TAP controller. The TAP controller involved in
this reset is determined according to the initial logical state applied on the JTAGSEL pin after
the last valid NRST.
In either Boundary Scan or ICE Mode, a reset can be performed from the same or different cir-
cuitry, as shown in
be asserted after each power-up. (See the AT91M42800A Electrical Datasheet, Atmel Lit. No.
1776, for the necessary minimum pulse assertion time.)
Figure 7-1.
Notes:
In order to benefit from the separation of NRST and NTRST during the debug phase of devel-
opment, the user must independently manage both signals as shown in example (1) of
7-1
ing production as shown in example (2) of
The internally generated watchdog reset has the same effect as the NRST pin, except that the
pins BMS and NTRI are not sampled. Boot mode and Tri-state mode are not updated. The
NRST pin has priority if both types of reset coincide.
The AT91M42800A provides a Tri-state mode, which is used for debug purposes in order to
connect an emulator probe to an application board. In Tri-state mode the AT91M42800A con-
tinues to function, but all the output pin drivers are tri-stated.
To enter Tri-state mode, the pin NTRI must be held low during the last 10 SLCK clock cycles
before the rising edge of NRST. For normal operation, the pin NTRI must be held high during
reset, by a resistor of up to 400 k . NTRI must be driven to a valid logic value during reset.
NTRI is multiplexed with Parallel I/O PA9 and USART 1 serial data transmit line TXD1.
above. However, once debug is completed, both signals are easily managed together dur-
Controller
Controller
1. NRST and NTRST handling in Debug Mode during development.
2. NRST and NTRST handling during production.
Reset
Reset
Separate or Common Reset Management
Figure 7-1
NTRST
NRST
AT91M42800A
below. But in all cases, the NTRST like the NRST signal, must
(1)
Figure 7-1
above.
Controller
Reset
AT91M42800A
NTRST
NRST
AT91M42800A
(2)
Figure
13