M42800A Atmel Corporation, M42800A Datasheet - Page 29

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

11.8
11.9
1779D–ATARM–14-Apr-06
Boot on NCS0
Read Protocols
Figure 11-8. Connection for a 16-bit Data Bus without Byte Write Capability
Depending on the device and the BMS pin level during the reset, the user can select either an
8-bit or 16-bit external memory device connected on NCS0 as the Boot memory. In this case,
EBI_CSR0 (Chip Select Register 0) is reset at the following configuration for chip select 0:
Byte access type and number of data float time are set to Byte Write Access and 0,
respectively.
Before the remap command, the user can modify the chip select 0 configuration, programming
the EBI_CSR0 with the exact Boot memory characteristics. The base address becomes effec-
tive after the remap command.
Warning: In the internal oscillator bypass mode described in
the user must take the external oscillator frequency into account according to the minimum
access time on the boot memory device.
As illustration, the following table gives examples of oscillator frequency limits according to the
time access without using NWAIT pin at the boot.
Note:
The EBI provides two alternative protocols for external memory read access: standard and
early read. The difference between the two protocols lies in the timing of the NRD (read cycle)
waveform.
Chip Select Assertion to Output Data Valid
Maximum Delay in Read Cycle (t
110
90
70
55
25
• 8 wait states (WSE = 0 - wait states disabled)
• 8-bit or 16-bit data bus width, depending on BMS
Values take only t
EBI
CE
D8 - D15
A1 - A19
into account.
D0 - D7
NCS2
NWE
NUB
NOE
NLB
CE
in ns)
D0 - D7
D8 - D15
A0 - A18
Write Enable
Output Enable
Memory Enable
Frequency Limit (MHz)
”Operating Modes” on page
External Oscillator
AT91M42800A
11
14
24
7
9
12,
29