M42800A Atmel Corporation, M42800A Datasheet - Page 200

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

• SCBR: Serial Clock Baud Rate (Code Label SP_SCBR)
In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the SPI Master Clock
(selected between MCK and MCK/32). The baud rate is selected by writing a value from 2 to 255 in the field SCBR. The fol-
lowing equation determines the SPCK baud rate:
Giving SCBR a value of zero or one disables the baud rate generator. SPCK is disabled and assumes its inactive state
value. No serial transfers may occur. At reset, baud rate is disabled.
• DLYBS: Delay Before SPCK (Code Label SP_DLYBS)
This field defines the delay from NPCS valid to the first valid SPCK transition.
When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.
Otherwise, the following equation determines the delay:
• DLYBCT: Delay Between Consecutive Transfers (Code Label SP_DLYBCT)
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
The delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, a delay of four SPI Master Clock periods are inserted.
Otherwise, the following equation determines the delay:
200
NPCS_to_SPCK_Delay = DLYBS • SPI_Master_Clock_period
Delay_After_Transfer = 32 • DLYBCT • SPI_Master_Clock_period
AT91M42800A
SPCK_Baud_Rate =
SPI_Master_Clock_frequency
2 x SCBR
1779D–ATARM–14-Apr-06