M42800A Atmel Corporation, M42800A Datasheet - Page 153

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

18.2.3
1779D–ATARM–14-Apr-06
Clock Control
Figure 18-2. Clock Selection
The clock of each counter can be controlled in two different ways: it can be enabled/disabled
and started/stopped.
• The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS
• The clock can also be started or stopped: a trigger (software, synchro, external or
commands in the Control Register. In Capture Mode it can be disabled by an RB load event
if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare
event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have
no effect: only a CLKEN command in the Control Register can re-enable the clock. When
the clock is enabled, the CLKSTA bit is set in the Status Register.
compare) always starts the clock. The clock can be stopped by an RB load event in
Capture Mode (LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode
(CPCSTOP = 1 in TC_CMR). The start and the stop commands have effect only if the clock
is enabled.
MCK/2
MCK/8
MCK/32
MCK/128
SLCK
XC0
XC1
XC2
1
CLKS
BURST
CLKI
Selected
Clock
AT91M42800A
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