M42800A Atmel Corporation, M42800A Datasheet - Page 164

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

18.9
Register Name:
Access Type:
Offset:
Reset Value:
• TCCLKS: Clock Selection
• CLKI: Clock Invert (Code Label TC_CLKI)
0 = Counter is incremented on rising edge of the clock.
1 = Counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
• LDBSTOP: Counter Clock Stopped with RB Loading (Code Label TC_LDBSTOP)
0 = Counter clock is not stopped when RB loading occurs.
1 = Counter clock is stopped when RB loading occurs.
• LDBDIS: Counter Clock Disable with RB Loading (Code Label TC_LDBDIS)
0 = Counter clock is not disabled when RB loading occurs.
1 = Counter clock is disabled when RB loading occurs.
164
WAVE=0
LDBDIS
0
0
0
0
1
1
1
1
31
23
15
0
0
1
1
–
–
7
TC Channel Mode Register: Capture Mode
AT91M42800A
TCCLKS
BURST
0
0
1
1
0
0
1
1
LDBSTOP
CPCTRG
30
22
14
TC_CMR
Read/Write
0x04
0x0
–
–
6
0
1
0
1
0
1
0
1
0
1
0
1
Clock Selected
MCK/2
MCK/8
MCK/32
MCK/128
SLCK
XC0
XC1
XC2
The clock is not gated by an external signal.
XC0 is ANDed with the selected clock.
XC1 is ANDed with the selected clock.
XC2 is ANDed with the selected clock.
Selected BURST
29
21
13
–
–
–
5
BURST
28
20
12
–
–
–
4
CLKI
27
19
11
–
–
3
LDRB
ABETRG
Code Label: TC_BURST
TC_BURST_NONE
TC_BURST_XC0
TC_BURST_XC1
TC_BURST_XC2
Code Label: TC_CLKS
TC_CLKS_MCK2
TC_CLKS_MCK8
TC_CLKS_MCK32
TC_CLKS_MCK128
TC_CLKS_SLCK
TC_CLKS_XC0
TC_CLKS_XC1
TC_CLKS_XC2
26
18
10
–
2
TCCLKS
25
17
–
9
1
ETRGEDG
1779D–ATARM–14-Apr-06
LDRA
24
16
–
8
0