M42800A Atmel Corporation, M42800A Datasheet - Page 212

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 24-3.
Note:
212
MCKI
NWAIT
NRD
1. These numbers refer to the standard access cycles.
AT91M42800A
Number of Standard Wait States is One
1 (1)
If the first two conditions are not met during a 32-bit read access, the first 16-bit data is read at
the end of the standard 16-bit read access. In the following example, the number of standard
waits is one. NWAIT assertions do affect both NRD pulse lengths, but first data sampling is not
delayed. The second data sampling is correct.
If the first two conditions are not met during write accesses, the NWE signal is not affected by
the NWAIT assertion. The following example illustrates the number of standard wait states.
NWAIT is not asserted during the first cycle, but is asserted at the second and last cycle of the
standard access. The access is correctly delayed as the NCS line rises accordingly to the
NWAIT assertion. However, the NWE signal waveform is unchanged, and rises too early.
EB16
32-bit Access = Two 16-bit Accesses
Each Access Length = One Wait State + Assertion for One More Cycle
2 (1)
First Data Sampling
(Erroneous)
2 (1)
1 (1)
2 (1)
2 (1)
1779D–ATARM–14-Apr-06
Second Data
Sampling
(Correct)