M42800A Atmel Corporation, M42800A Datasheet - Page 96

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

14.26 Fast Interrupt Sequence
96
AT91M42800A
Note:
It is assumed that:
When NFIQ is asserted, if the F-bit of CPSR is 0, the sequence is:
Note:
9. The SPSR (SPSR_irq) is restored. Finally, the saved value of the Link Register is
• The Advanced Interrupt Controller has been programmed, AIC_SVR[0] is loaded with fast
• The Instruction at address 0x1C(FIQ exception vector address) is:
• Nested Fast Interrupts are not needed by the user.
1. The CPSR is stored in SPSR_fiq, the current value of the Program Counter is loaded
2. The ARM core enters FIQ mode.
3. When the instruction loaded at address 0x1C is executed, the Program Counter is
4. The previous step has effect to branch to the corresponding interrupt service routine.
5. The Interrupt Handler can then proceed as required. It is not necessary to save regis-
6. Finally, the Link Register (R14_fiq) is restored into the PC after decrementing it by 4
interrupt service routine address and the fast interrupt is enabled.
ldr pc, [pc, #-&F20]
restored directly into the PC. This has effect of returning from the interrupt to what-
ever was being executed before, and of loading the CPSR with the stored SPSR,
masking or unmasking the interrupts depending on the state saved in the SPSR (the
previous state of the ARM core).
in the FIQ link register (R14_fiq) and the Program Counter (R15) is loaded with 0x1C.
In the following cycle, during fetch at address 0x20, the ARM core adjusts R14_fiq,
decrementing it by 4.
loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automat-
ically clearing the fast interrupt (source 0 connected to the FIQ line), if it has been
programmed to be edge triggered. In this case only, it de-asserts the NFIQ line on the
processor.
It is not necessary to save the Link Register(R14_fiq) and the SPSR(SPSR_fiq) if
nested fast interrupts are not needed.
ters R8 to R13 because FIQ mode has its own dedicated registers and the user R8 to
R13 are banked. The other registers, R0 to R7, must be saved before being used,
and restored at the end (before the next step). Note that if the fast interrupt is pro-
grammed to be level sensitive, the source of the interrupt must be cleared during this
phase in order to de-assert the NFIQ line.
(with instruction sub pc, lr, #4 for example). This has effect of returning from the inter-
rupt to whatever was being executed before, and of loading the CPSR with the SPSR,
masking or unmasking the fast interrupt depending on the state saved in the SPSR.
The I-bit in the SPSR is significant. If it is set, it indicates that the ARM core was just about to
mask IRQ interrupts when the mask instruction was interrupted. Hence, when the SPSR is
restored, the mask instruction is completed (IRQ is masked).
The F-bit in the SPSR is significant. If it is set, it indicates that the ARM core was just about to
mask FIQ interrupts when the mask instruction was interrupted. Hence when the SPSR is
restored, the interrupted instruction is completed (FIQ is masked).
1779D–ATARM–14-Apr-06