M42800A Atmel Corporation, M42800A Datasheet - Page 180

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Table 19-1.
Notes:
19.2
19.2.1
180
Pin Name
Master In Slave Out
Master Out Slave In
Serial Clock
Peripheral Chip Selects
Peripheral Chip Select/
Slave Select
1. After a hardware reset, the SPI clock is disabled by default (see
2. After a hardware reset, the SPI pins are deselected by default (see
Master Mode
AT91M42800A
Fixed Peripheral Select
user must configure the Power Management Controller before any access to the User Interface of the SPI.
configure the PIO Controller to enable the corresponding pins for their SPI function. NPCS0/NSS must be configured as
open-drain in the Parallel I/O Controller for multi-master operation.
SPI Pins
In Master mode, the SPI controls data transfers to and from the slave(s) connected to the SPI
bus. The SPI drives the chip select(s) to the slave(s) and the serial clock (SPCK). After
enabling the SPI, a data transfer begins when the ARM core writes to the SP_TDR (Transmit
Data Register). See
Transmit and Receive buffers maintain the data flow at a constant rate with a reduced require-
ment for high priority interrupt servicing. When new data is available in the SP_TDR (Transmit
Data Register) the SPI continues to transfer data. If the SP_RDR (Receive Data Register) has
not been read before new data is received, the Overrun Error (OVRES) flag is set.
The delay between the activation of the chip select and the start of the data transfer (DLYBS)
as well as the delay between each data transfer (DLYBCT) can be programmed for each of
the four external chip selects. All data transfer characteristics including the two timing values
are programmed in registers SP_CSR0 to SP_CSR3 (Chip Select Registers). See
on page
In master mode the peripheral selection can be defined in two different ways:
Figures 19-2 and 19-3 show the operation of the SPI in Master mode. For details concerning
the flag and control bits in these diagrams, see the tables in
Model” on page
This mode is ideal for transferring memory blocks without the extra overhead in the transmit
data register to determine the peripheral.
• Fixed Peripheral Select: SPI exchanges data with only one peripheral
• Variable Peripheral Select: Data can be exchanged with more than one peripheral
82.
Mnemonic
Generic
NPCS1-
NPCS0/
NPCS3
SPCK
MISO
MOSI
NSS
187.
Table 14-1 on page
Master
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
”PMC: Power Management Controller” on page
82.
Function
Serial data input to SPI
Serial data output from SPI
Serial data output from SPI
Serial data input to SPI
Clock output from SPI
Clock input to SPI
Select peripherals
Output: Selects peripheral
Input: low causes mode fault
Input: chip select for SPI
”PIO: Parallel I/O Controller” on page
Section 19.7 ”SPI Programmer’s
1779D–ATARM–14-Apr-06
97). The user must
Table 14-1
55). The