M42800A Atmel Corporation, M42800A Datasheet - Page 210

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

24. AT91M42800A Errata
24.1
210
Warning: Additional NWAIT Constraints
AT91M42800A
These errata are applicable to:
When the NWAIT signal is asserted during an external memory access, the following EBI
behavior is correct:
In these cases, the access is delayed as required by NWAIT and the access operations are
correctly performed.
In other cases, the following erroneous behavior occurs:
At maximum speed, asserting the NWAIT in the first access cycle is not possible, as the sum
of the timings “MCKI Falling to Chip Select” and “NWAIT setup to MCKI rising” are generally
higher than one half of a clock period. This leads to using at least one standard wait state.
However, this is not sufficient except to perform byte or half-word read accesses. Word and
write accesses require at least two standard wait states.
The following waveforms further explain the issue:
• 144-lead TQFP and 144-ball BGA devices with the following markings:
• NWAIT is asserted before the first rising edge of the master clock and respects the NWAIT
• NWAIT is sampled inactive and at least one standard wait state remains to be executed,
• 32-bit read accesses are not managed correctly and the first 16-bit data sampling takes
• During write accesses of any type, the NWE rises on the rising edge of the last cycle as
to MCKI rising setup timing as defined in the Electrical Characteristics datasheet.
even if NWAIT does not meet the NWAIT to first MCKI rising setup timing (i.e., NWAIT is
asserted only on the second rising edge of MCKI).
into account only the standard wait states. 16- and 8-bit accesses are not affected.
defined by the programmed number of wait states. However, NWAIT assertion does affect
the length of the total access. Only the NWE pulse length is inaccurate.
Internal Product
Reference 56544C
AT91M42800A-33CJ
AT91M42800A-33AU
1779D–ATARM–14-Apr-06