M42800A Atmel Corporation, M42800A Datasheet - Page 71

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

13. ST: System Timer
13.1
13.2
1779D–ATARM–14-Apr-06
PIT: Period Interval Timer
WDT: Watchdog Timer
The System Timer module integrates three different free-running timers:
These timers count using the Slow Clock. Typically, this clock has a frequency of 32.768 kHz.
Figure 13-1. System Timer Module
The Period Interval Timer can be used to provide periodic interrupts for use by operating sys-
tems. It is built around a 16-bit down counter, which is preloaded by a value programmed in
ST_PIMR (Period Interval Mode Register). When the PIT counter reaches 0, the bit PITS is
set in ST_SR (Status Register), and an interrupt is generated, if it is enabled.
The counter is then automatically reloaded and restarted. Writing to the ST_PIMR at any time
immediately reloads and restarts the down counter with the new programmed value.
Figure 13-2. Period Interval Timer
Note:
The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped
in a deadlock.
It is built around a 16-bit down counter loaded with the value defined in ST_WDMR (Watchdog
Mode Register). It uses the Slow Clock divided by 128. This allows the maximum watchdog
period to be 256 seconds (with a typical Slow Clock of 32.768 kHz).
In normal operation, the user reloads the watchdog at regular intervals before the timer over-
flow occurs. This is done by writing to the ST_CR (Control Register) with the bit WDRST set.
• A Period Interval Timer setting the base time for an Operating System.
• A Watchdog Timer having capabilities to reset the system in case of software deadlock.
• A Real-time Timer counting elapsed seconds.
If ST_PIMR is programmed with a period less or equal to the current MCK period, the update of
the PITS status bit and its associated interrupt generation are unpredictable.
Slow Clock
Interface
Slow Clock
SLCK
APB
SLCK
Down Counter
System
Module
Timer
16-bit
PIV
Period Interval
Value
STIRQ
System Timer Interrupt
NWDOVF
PITS
Period Interval
Timer Status
AT91M42800A
71