M42800A Atmel Corporation, M42800A Datasheet - Page 110

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

15.20 PIO Output Data Status Register
Register Name:
Access Type:
Offset:
Reset Value:
This register shows the output data status which is programmed in PIO_SODR or PIO_CODR. The defined value is effec-
tive only if the pin is controlled by the PIO Controller and only if the pin is defined as an output.
0 = The output data for the corresponding line is programmed to 0.
1 = The output data for the corresponding line is programmed to 1.
15.21 PIO Pin Data Status Register
Register Name:
Access Type:
Offset:
Reset Value:
This register shows the state of the physical pin of the chip. The pin values are always valid, regardless of whether the pins
are enabled as PIO, peripheral, input or output. The register reads as follows:
0 = The corresponding pin is at logic 0.
1 = The corresponding pin is at logic 1.
110
P31
P23
P15
P31
P23
P15
31
23
15
P7
31
23
15
P7
7
7
AT91M42800A
P30
P22
P14
P30
P22
P14
P6
P6
PIO_ODSR
Read-only
0x38
0
30
22
14
PIO_PDSR
Read-only
0x3C
Undefined
30
22
14
6
6
P29
P21
P13
P29
P21
P13
29
21
13
P5
29
21
13
P5
5
5
P28
P20
P12
P28
P20
P12
P4
P4
28
20
12
28
20
12
4
4
P27
P19
P11
P27
P19
P11
P3
P3
27
19
11
27
19
11
3
3
P26
P18
P10
P26
P18
P10
P2
P2
26
18
10
26
18
10
2
2
P25
P17
P25
P17
P9
P1
P9
P1
25
17
25
17
9
1
9
1
1779D–ATARM–14-Apr-06
P24
P16
P24
P16
P8
P0
P8
P0
24
16
24
16
8
0
8
0