M42800A Atmel Corporation, M42800A Datasheet - Page 160

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

18.5
TC Block 0 Base Address: 0xFFFD0000 (Code Label TCB0_BASE)
TC Block 1 Base Address: 0xFFFD4000 (Code Label TCB1_BASE)
Table 7. TC Global Memory Map
TC_BCR (Block Control Register) and TC_BMR (Block Mode Register) control the TC block. TC Channels are controlled
by the registers listed in Table 8. The offset of each of the Channel registers in Table 8 is in relation to the offset of the cor-
responding channel as mentioned in Table 7.
Table 8. TC Channel Memory Map
Note:
160
Offset
Offset
0xC0
0xC4
0x0C
0x1C
0x2C
0x00
0x40
0x80
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
TC User Interface
1. Read-only if WAVE = 0
AT91M42800A
TC Block Control Register
Channel/Register
TC Channel 0
TC Channel 1
TC Channel 2
TC Block Mode Register
Register
Channel Control Register
Channel Mode Register
Reserved
Reserved
Counter Value
Register A
Register B
Register C
Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
TC_BMR
TC_CCR
TC_CMR
TC_BCR
TC_IMR
TC_IER
TC_IDR
TC_CV
TC_RA
TC_RB
TC_RC
TC_SR
Name
Name
Read/Write
Read/Write
See Table 8
See Table 8
See Table 8
Read/Write
Read/Write
Read/Write
Read/Write
Read-only
Read-only
Write-only
Write-only
Write-only
Write-only
Access
Access
(1)
(1)
1779D–ATARM–14-Apr-06
Reset State
Reset State
–
0
–
0
–
–
0
0
0
0
–
–
–
0