M42800A Atmel Corporation, M42800A Datasheet - Page 189

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

19.9
Register Name:
Access Type:
Offset:
Reset Value:
• MSTR: Master/Slave Mode (Code Label SP_MSTR)
0 = SPI is in Slave mode.
1 = SPI is in Master mode.
MSTR configures the SPI Interface for either master or slave mode operation.
• PS: Peripheral Select
• PCSDEC: Chip Select Decode (Code Label SP_PCSDEC)
0 = The chip selects are directly connected to a peripheral device.
1 = The four chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals one, up to 16 Chip Select signals can be generated with the four lines using an external 4- to 16-bit
decoder.
The Chip Select Registers define the characteristics of the 16 chip selects according to the following rules:
Note:
• MCK32: Clock Selection (Code Label SP_DIV32)
0 = SPI Master Clock equals MCK
1 = SPI Master Clock equals MCK/32
• LLB: Local Loopback Enable (Code Label SP_LLB)
0 = Local loopback path disabled
1 = Local loopback path enabled
LLB controls the local loopback on the data serializer for testing in master mode only.
• PCS: Peripheral Chip Select (Code Label SP_PCS)
1779D–ATARM–14-Apr-06
PS
0
1
LLB
SP_CSR0 defines peripheral chip select signals 0 to 3.
SP_CSR1 defines peripheral chip select signals 4 to 7.
SP_CSR2 defines peripheral chip select signals 8 to 11.
SP_CSR3 defines peripheral chip select signals 12 to 15
31
23
15
–
–
7
SPI Mode Register
1. The 16th state corresponds to a state in which all chip selects are inactive. This allows a different clock configuration to be
defined by each chip select register.
30
22
14
SP_MR
Read/Write
0x04
0x0
–
–
6
–
Selected PS
Fixed Peripheral Select
Variable Peripheral Select
29
21
13
–
–
5
–
28
20
12
–
–
4
–
DLYBCS
(1)
.
MCK32
27
19
11
–
3
Code Label: SP_PS
SP_PS_FIXED
SP_PS_VARIABLE
PCSDEC
26
18
10
–
2
PCS
AT91M42800A
PS
25
17
9
–
1
MSTR
24
16
8
–
0
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