M42800A Atmel Corporation, M42800A Datasheet - Page 97

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

15. PIO: Parallel I/O Controller
15.1
15.2
15.3
15.4
1779D–ATARM–14-Apr-06
Multiplexed I/O Lines
Output Selection
I/O Levels
Filters
The AT91M42800A has 54 programmable I/O lines. I/O lines are multiplexed with an external
signal of a peripheral to optimize the use of available package pins (see Tables
page 100
cal PIO Controllers called PIOA and PIOB. Each PIO controller also provides an internal
interrupt signal to the Advanced Interrupt Controller.
Note:
When a peripheral signal is not used in an application, the corresponding pin can be used as a
parallel I/O. Each parallel I/O line is bi-directional, whether the peripheral defines the signal as
input or output. Figure 15-1 shows the multiplexing of the peripheral signals with Parallel I/O
signals.
A pin is controlled by the registers PIO_PER (PIO Enable) and PIO_PDR (PIO Disable). The
register PIO_PSR (PIO Status) indicates whether the pin is controlled by the corresponding
peripheral or by the PIO Controller.
When the PIO is selected, the peripheral input line is connected to zero.
The user can enable each individual I/O signal as an output with the registers PIO_OER (Out-
put Enable) and PIO_ODR (Output Disable). The output status of the I/O signals can be read
in the register PIO_OSR (Output Status). The direction defined has effect only if the pin is con-
figured to be controlled by the PIO Controller.
Each pin can be configured to be driven high or low. The level is defined in four different ways,
according to the following conditions.
In all cases, the level on the pin can be read in the register PIO_PDSR (Pin Data Status).
Optional input glitch filtering is available on each pin and is controlled by the registers
PIO_IFER (Input Filter Enable) and PIO_IFDR (Input Filter Disable). The input glitch filtering
can be selected whether the pin is used for its peripheral function or as a parallel I/O line. The
register PIO_IFSR (Input Filter Status) indicates whether or not the filter is activated for each
pin.
• If a pin is controlled by the PIO Controller and is defined as an output (see
• If a pin is controlled by the PIO Controller and is not defined as an output, the level is
• If a pin is not controlled by the PIO Controller, the state of the pin is defined by the
”Output Selection” on page 97
PIO_SODR (Set Output Data) and PIO_CODR (Clear Output Data). In this case, the
programmed value can be read in PIO_ODSR (Output Data Status).
determined by the external circuit.
peripheral (see peripheral datasheets).
After a hardware reset, the PIO clock is disabled by default (see
agement Controller” on page
before any access to the User Interface of the PIO.
and
Table 15-2 on page
above), the level is programmed using the registers
101). These lines are controlled by two separate and identi-
55). The user must configure the Power Management Controller
Section 12. ”PMC: Power Man-
AT91M42800A
Section 15.2
Table 15-1 on
97