M42800A Atmel Corporation, M42800A Datasheet - Page 26
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
M42800A
Manufacturer Part Number
M42800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M42800A.pdf
(224 pages)
4.M42800A.pdf
(27 pages)
Specifications of M42800A
Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
54
Usb Speed
No
Usb Interface
No
Spi
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Boot on NCS0
26
AT91X40 Series
Depending on the device and the BMS pin level during the reset, the user can select
either an 8-bit or 16-bit external memory device connected on NCS0 as the Boot Mem-
ory. In this case, EBI_CSR0 (Chip Select Register 0) is reset at the following
configuration for chip select 0:
•
•
Byte access type and number of data float time are respectively set to Byte Write
Access and 0. With a non-volatile memory interface, any values can be programmed for
these parameters.
Before the remap command, the user can modify the chip select 0 configuration, pro-
gramming the EBI_CSR0 with exact boot memory characteristics. the base address
becomes effective after the remap command, but the new number of wait states can be
changed immediately. This is useful if a boot sequence needs to be faster.
8 wait states (WSE = 1, NWS = 7)
8-bit or 16-bit data bus width, depending on BMS
1354D–ATARM–08/02
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