M42800A Atmel Corporation, M42800A Datasheet - Page 24
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M42800A
Manufacturer Part Number
M42800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M42800A.pdf
(224 pages)
4.M42800A.pdf
(27 pages)
Specifications of M42800A
Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
54
Usb Speed
No
Usb Interface
No
Spi
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Byte Write or Byte Select
Access
24
AT91X40 Series
Each chip select with a 16-bit data bus can operate with one of two different types of
write access:
•
•
This option is controlled by the BAT field in the EBI_CSR (Chip Select Register) for the
corresponding chip select.
Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory page.
•
•
•
•
Figure 11 shows how to connect two 512K x 8-bit devices in parallel on NCS2.
Figure 11. Memory Connection for 2 x 8-bit Data Busses
Byte Write Access supports two byte write and a single read signal.
Byte Select Access selects upper and/or lower byte with two byte select lines, and
separate read and write signals.
The signal A0/NLB is not used.
The signal NWR1/NUB is used as NWR1 and enables upper byte writes.
The signal NWR0/NWE is used as NWR0 and enables lower byte writes.
The signal NRD/NOE is used as NRD and enables half-word and byte reads.
EBI
D8 - D15
A1 - A19
D0 - D7
NWR1
NWR0
NCS2
NRD
A0
D0 - D7
A0 - A18
Write Enable
Read Enable
Memory Enable
D8 - D15
A0 - A18
Write Enable
Read Enable
Memory Enable
1354D–ATARM–08/02
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