SAM3N1A Atmel Corporation, SAM3N1A Datasheet - Page 204

• Manufacturer Part Number: SAM3N1A
• Manufacturer: Atmel Corporation

Specifications of SAM3N1A

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

11.5
11.5.1
11.5.2
Figure 11-4. Debug Architecture
11.5.3
204
Functional Description
data address sampler
SAM3N
Test Pin
Debug Architecture
Serial Wire/JTAG Debug Port (SWJ-DP)
4 watchpoints
interrupt trace
data sampler
CPU statistics
PC sampler
DWT
One dedicated pin, TST, is used to define the device operating mode. When this pin is at low
level during power-up, the device is in normal operating mode. When at high level, the device is
in test mode or FFPI mode. The TST pin integrates a permanent pull-down resistor of about 15
kΩ, so that it can be left unconnected for normal operation. Note that when setting the TST pin to
low or high level at power up, it must remain in the same state during the duration of the whole
operation.
Figure 11-4
tional units for debug:
The debug architecture information that follows is mainly dedicated to developers of SWJ-DP
Emulators/Probes and debugging tool vendors for Cortex M3-based microcontrollers. For further
details on SWJ-DP see the Cortex M3 technical reference manual.
The Cortex-M3 embeds a SWJ-DP Debug port which is the standard CoreSight
combines Serial Wire Debug Port (SW-DP), from 2 to 3 pins and JTAG debug Port(JTAG-DP), 5
pins.
By default, the JTAG Debug Port is active. If the host debugger wants to switch to the Serial
Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and
TCK/SWCLK which disables JTAG-DP and enables SW-DP.
• SWJ-DP (Serial Wire/JTAG Debug Port)
• FPB (Flash Patch Breakpoint)
• DWT (Data Watchpoint and Trace)
• ITM (Instrumentation Trace Macrocell)
• TPIU (Trace Port Interface Unit)
shows the Debug Architecture used in the SAM3. The Cortex-M3 embeds four func-
software trace
time stamping
6 breakpoints
32 channels
FPB
ITM
TPIU
SWD/JTAG
SWO trace
SWJ-DP
11011A–ATARM–04-Oct-10
™
debug port. It