SAM3N1A Atmel Corporation, SAM3N1A Datasheet - Page 663
SAM3N1A
Manufacturer Part Number
SAM3N1A
Description
Manufacturer
Atmel Corporation
Specifications of SAM3N1A
Flash (kbytes)
64 Kbytes
Pin Count
48
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
17
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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33.7.3
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in
• USCHx: User Sequence Number x
The sequence number x (USCHx) can be programmed by the Channel number CHy where y is the value written in this
field. The allowed range is 0 up to 15. So it is only possible to use the sequencer from CH0 to CH15.
This register activates only if ADC_MR(USEQ) field is set to ‘1’.
Any USCHx field is taken into account only if ADC_CHSR(CHx) register field reads logical ‘1’ else any value written in
USCHx does not add the corresponding channel in the conversion sequence.
Configuring the same value in different fields leads to multiple samples of the same channel during the conversion
sequence. This can be done consecutively, or not, according to user needs.
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
31
23
15
7
ADC Channel Sequence 1 Register
30
22
14
ADC_SEQR1
0x40038008
Read-write
6
USCH8
USCH6
USCH4
USCH2
29
21
13
5
28
20
12
4
“ADC Write Protect Mode Register” on page
27
19
11
3
26
18
10
2
USCH7
USCH5
USCH3
USCH1
25
17
9
1
677.
SAM3N
SAM3N
24
16
8
0
663
663
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