SAM3N4C Atmel Corporation, SAM3N4C Datasheet - Page 39

• Manufacturer Part Number: SAM3N4C
• Manufacturer: Atmel Corporation

Specifications of SAM3N4C

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 24
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10. ARM Cortex
10.1
10.2
10.3
11011A–ATARM–04-Oct-10
About this section
Embedded Characteristics
About the Cortex-M3 processor and core peripherals
®
M3 Processor
This section provides the information required for application and system-level software devel-
opment. It does not provide information on debug components, features, or operation.
This material is for microcontroller software and hardware engineers, including those who have
no experience of ARM products.
Note: The information in this section is reproduced from source material provided to Atmel by
ARM Ltd. in terms of Atmel’s license for the ARM Cortex
copyright ARM Ltd., 2008 - 2009.
Processor state automatically saved on interrupt entry and restored on interrupt exit, with no
instruction overhead
• Version 2.0
• Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit.
• Harvard processor architecture enabling simultaneous instruction fetch with data load/store.
• Three-stage pipeline.
• Single cycle 32-bit multiply.
• Hardware divide.
• Thumb and Debug states.
• Handler and Thread modes.
• Low latency ISR entry and exit.
• SysTick Timer
• Nested Vectored Interrupt Controller
• The Cortex-M3 processor is a high performance 32-bit processor designed for the
• outstanding processing performance combined with fast interrupt handling
microcontroller market. It offers significant benefits to developers, including:
– 24-bit down counter
– Self-reload capability
– Flexible System timer
– Thirty Two maskable external interrupts
– Sixteen priority levels
– Processor state automatically saved on interrupt entry, and restored on
– Dynamic reprioritization of interrupts
– Priority grouping
– Support for tail-chaining and late arrival of interrupts
back-to-back interrupt processing without the overhead of state saving and restoration
between interrupts.
selection of pre-empting interrupt levels and non pre-empting interrupt levels
®
-M3 processor core. This information is
SAM3N
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