SAM3N4C Atmel Corporation, SAM3N4C Datasheet - Page 639

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SAM3N4C

Manufacturer Part Number
SAM3N4C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3N4C

Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
24
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
32.7.1
Name:
Address:
Access:
• DIVA, DIVB: CLKA, CLKB Divide Factor
• PREA, PREB
Values which are not listed in the table must be considered as “reserved”.
11011A–ATARM–04-Oct-10
Value
0
1
2-255
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
31
23
15
7
PWM Mode Register
CLK_OFF
CLK_DIV1
MCK
MCKDIV2
MCKDIV4
MCKDIV8
MCKDIV16
MCKDIV32
MCKDIV64
MCKDIV128
MCKDIV256
MCKDIV512
MCKDIV1024
30
22
14
0x40020000
6
PWM_MR
Read/Write
Name
Name
29
21
13
5
Master Clock
Master Clock divided by 2
Master Clock divided by 4
Master Clock divided by 8
Master Clock divided by 16
Master Clock divided by 32
Master Clock divided by 64
Master Clock divided by 128
Master Clock divided by 256
Master Clock divided by 512
Master Clock divided by 1024
CLKA, CLKB clock is turned off
CLKA, CLKB clock is clock selected by PREA, PREB
CLKA, CLKB clock is clock selected by PREA, PREB
divided by DIVA, DIVB factor.
28
20
12
4
DIVB
DIVA
Description
Description
27
19
11
3
26
18
10
2
PREB
PREA
25
17
9
1
SAM3N
24
16
8
0
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