SAM3N4C Atmel Corporation, SAM3N4C Datasheet - Page 90
SAM3N4C
Manufacturer Part Number
SAM3N4C
Description
Manufacturer
Atmel Corporation
Specifications of SAM3N4C
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
24
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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SAM3N
Post-indexed addressing
Restrictions
Condition flags
The address obtained from the register Rn is used as the address for the memory access. The
offset value is added to or subtracted from the address, and written back into the register Rn.
The assembly language syntax for this mode is:
The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can
either be signed or unsigned. See
Table 10-18
Table 10-18. Offset ranges
For load instructions:
When Rt is PC in a word load instruction:
For store instructions:
These instructions do not change the flags.
Instruction type
Word, halfword, signed
halfword, byte, or signed
byte
Two words
• Rt can be SP or PC for word loads only
• Rt must be different from Rt2 for two-word loads
• Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
• bit[0] of the loaded value must be 1 for correct execution
• a branch occurs to the address created by changing bit[0] of the loaded value to 0
• if the instruction is conditional, it must be the last instruction in the IT block.
• Rt can be SP for word stores only
• Rt must not be PC
• Rn must not be PC
• Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
[Rn, #offset]!
[Rn], #offset
shows the ranges of offset for immediate, pre-indexed and post-indexed forms.
Immediate offset
− 255 to 4095
multiple of 4 in the
range − 1020 to
1020
“Address alignment” on page
Pre-indexed
− 255 to 255
multiple of 4 in the
range − 1020 to
1020
83.
Post-indexed
− 255 to 255
multiple of 4 in the
range − 1020 to
1020
11011A–ATARM–04-Oct-10
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