SAM9261 Atmel Corporation, SAM9261 Datasheet - Page 704

• Manufacturer Part Number: SAM9261
• Manufacturer: Atmel Corporation

Specifications of SAM9261

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 160
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

42.2.15.3
42.2.15.4
42.2.15.5
42.2.15.6
42.2.16
42.2.16.1
704
AT91SAM9261
UDP
TWI: NACK Status Bit Lost
TWI: Possible Receive Holding Register Corruption
TWI: Software reset
TWI: STOP not generated
UDP: Bad data in the first IN data stage
During a master frame, if TWI_SR is read between the Non Acknowledge condition detection
and the TXCOMP bit rising in the TWI_SR, the NACK bit is not set.
The user must wait for the TXCOMP status bit by interrupt and must not read the TWI_SR as
long as transmission is not completed.
Note:
When loading the TWI_RHR, the transfer direction is ignored. The last data byte received in the
TWI_RHR is corrupted at the end of the first subsequent transmit data byte. Neither RXRDY nor
OVERRUN status bits are set if this occurs.
The user must be sure that received data is read before transmitting any new data.
When a software reset is performed during a frame and when TWCK is low, it is impossible to
initiate a new transfer in READ or WRITE mode.
None.
If the sequence described as follows occurs:
then STOP is not generated.
The line will show: DADR BYTE 1, ..., BYTE n, NO STOP generated, BYTE 1, ..., BYTE n.
Insert a delay of one TWI clock period before step 4 in the sequence above.
All or part of the data of the first IN data Stage are not transmitted.It may then be a Zero Length
Packet. The CRC is correct. So the HOST may only see that the size of the received data does
not match the requested length. But even if performed again, the control transfer will probably
fail.
These Control transfers are mainly used at device configuration. After clearing RXSETUP, the
software needs to compute the setup transaction request before writing data into the FIFO if
needed. This time is generally greater than the minimum safe delay required above. If not, a
software wait loop after RXSETUP clear may be added at minimum cost
1. WRITE 1 or more bytes at a given address.
2. Send a STOP.
3. Wait for TXCOMP flag.
4. READ (or WRITE) 1 or more bytes at the same address.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
TXCOMP and NACK fields are set simultaneously and the NACK field is reset after the read of the
TWI_SR.
6062N–ATARM–3-Oct-11